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galileo gt-482xx gt-48212 / gt-48208 / GT-48207 advanced switched ethernet controllers for 10+10/100 basex preliminary revision 1.2 1/27/99 features www.galileot.com info@galileot.com tel: 408-367-1400 fax: 408-367-1401 galileo technology confidential -- do not reproduce please contact galileo technolo g y for possible updates before finalizin g a desi g n. ?sin g le-chip switched ethernet controllers for 10 and 10/100base-x - provides packet switching functions between eight or 12 ethernet ports and two auto- negotiated on-chip fast ethernet ports - switch expansion via fast mii port ? three versions for different cost/performance points - gt-48212: 12 10baset ports, two 100basex ports and advanced management features - gt-48208: eight 10baset ports, two 100basex ports and advanced management features - GT-48207: eight 10baset ports, two 100basex ports with no management features ? low-cost 32-bit cpu interface for mana g ement - glueless interface to idt 3041, motorola coldfire, intel i960?r/jx cpus, and gt-641xx controllers. - simple interface to other 32/64-bit cpus ? mana g ement cpu not required - allows for cost sensitive unmanaged designs ?ei g ht or twelve 802.3 compliant ethernet ports - 10mbps half-duplex or 20mbps full-duplex - serial mode selectable per port: 10base-t or fl ? two fast ethernet media access controllers - direct interface to mii - half/full duplex support - ieee 802.3 100base-tx, t4, and fx compatible - full mii management support (mdc/mdio) - auto-negotiation supported through mii interface ? flow control on all ports - standard 802.3x flow control for full duplex mode - back pressure for half duplex mode ? direct support for packet bufferin g - 1mbyte: using one device - 256kx32-bit synchronous graphics ram (sgdram) - 4mbyte: using two devices - 1mx16bit sdram - up to 2k buffers, 1536-bytes each, dynamically allocated to the receive queues and cpu ?hi g h observabilit y led interface - three pin serial led interface for additional status information per port ? advanced address reco g nition on-chip - intelligent address recognition mechanism enables forwarding rate at full wire speed - self-learning mechanism - supports up to 8k unicast addresses and unlimited multicast/broadcast addresses - multicast address support in address table - broadcast storm filtering ? extensive network mana g ement support - repeater mib counters allowing implementation of four rmon groups - hardware assist for spanning tree algorithm - cpu access to address table - cpu query - ability to read the information from the address table - ability to define static addresses - monitoring (sniffer) mode ?port lockin g for securit y ? automatic address a g in g support ?priorit y queuin g based on mac address or 802.1q ta g ? port and mac address based vlan ? ip multicast support ? flexible software or hardware intervention in packet routin g decisions ? packet samplin g mana g ement technolo gy
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 2 revision 1.2 - takes snapshots of packets and counters at programmable intervals - allows for the implementation of hp-ease or sampled rmon with low-cost cpus ? 12 general purpose output pins ( leds, etc. ) ? 3.3v with 5v tolerant i/os ? 208 pin pqfp packa g e block dia g ram of t y pical mana g ed switch ( two 100 mbit ports + 12 10 mbit ports ) cpu bus ( when cpu present ) cpu (optional) 12 x 10baset 2 x 100basetx gt-48212 sdram 10baset filters 100basetx phy/xcvr cpu bus ( when cpu present ) gt-48212 sdram 10baset filters 12 x 10baset 100basetx phy/xcvr 1 x 100basetx gt-48212 sdram 10baset filters 12 x 10baset 100basetx phy/xcvr 1 x 100basetx fast mii cpu (optional) block dia g ram of t y pical mana g ed switch ( two 100 mbit ports + 24 10 mbit ports )
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 3 table of contents 1. general description ..................................................................................................... 9 1.1 fast ethernet ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 ethernet ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 flow control and back pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 s y nchronous gram/dram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 address reco g nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 ip multicast and vlan support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.8 priorit y queuein g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.9 network mana g ement features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.10 differences between the gt-48212, gt-48208 and GT-48207 . . . . . . . . . . . . . . . . . . . 12 2. pinout ....................................................................................................................... ... 13 2.1 pin functions and assi g nment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. galax y famil y overview ............................................................................................ 19 3.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 address learnin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 packet bufferin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 packet forwardin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 terminolo gy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. microarchitectural overview ..................................................................................... 21 5. buffers and queues ................................................................................................... 23 5.1 rx buffer threshold pro g rammin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 head-of-line blockin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. mac address table ................................................................................................... 26 6.1 forwardin g mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 address learnin g process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 locked port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 address entr y update and quer y from cpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.6 address reco g nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7 address a g in g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8 static addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.9 address reco g nition failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.10 forwardin g priorit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. packet forwardin g ..................................................................................................... 33 7.1 forwardin g a unicast packet to a local port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 forwardin g a multicast packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3 forwardin g a packet to the cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4 forwardin g a packet from the cpu to the gt-482xx . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.5 intervention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.6 igmp packet support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7 crc generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.8 tx watchdo g timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 4 revision 1.2 8. fast ethernet interfaces ............................................................................................ 37 8.1 10/100 mii compatible interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.2 media access control ( mac ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.3 auto-ne g otiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.4 backoff al g orithm options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.5 data blinder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6 inter-packet gap ( ipg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.7 10/100 mbps mii transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.8 10/100 mbps mii reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.9 10/100 mbps full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.10 ille g al frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.11 partition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.12 back pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.13 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.14 802.1 q vlan ta gg in g support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.15 mii mana g ement interface ( smi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.16 link detection and link detection b y pass ( forcelinkpass ) . . . . . . . . . . . . . . . . . . . . . . 43 8.17 usin g the mii interfaces to connect two ( or more ) galax y devices . . . . . . . . . . . . . . . . 44 9. ethernet (10mbps) interfaces.................................................................................... 45 9.1 media access control ( mac ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 ille g al frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 duplex mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4 backoff al g orithm options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5 manchester encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6 link inte g rit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.7 data blinder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8 inter-packet gap ( ipg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.9 partition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.10 802.1 q vlan ta gg in g support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.11 back pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.12 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.13 serial modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.14 ph y sical interface circuitr y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.15 serial link status indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 10. enablin g /disablin g ports........................................................................................... 48 11. network mana g ement support ................................................................................. 49 11.1 repeater mib counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 monitorin g ( sniffer ) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3 spannin g tree ( bpdu ) support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.4 broadcast storm filterin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12. packet samplin g technolo gy (hp-ease) ................................................................ 51 12.1 packet samplin g overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2 ease functionalit y on the gt-482xx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.3 ease re g ister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.4 ease interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.5 sampled packet indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 5 12.6 error source indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.7 enablin g /disablin g ease functionalit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13. led support ............................................................................................................... 54 13.1 led indications interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.2 detailed led si g nal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.3 led si g nal timin g t y pes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.4 led interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 14. interrupts .................................................................................................................. .. 65 15. reset confi g uration................................................................................................. 66 15.1 confi g uration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 15.2 confi g uration input timin g s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 16. cpu hardware interface and address mappin g ...................................................... 69 16.1 re g ister and memor y mappin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.2 cpu interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 16.3 cpu interface pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.4 selectin g the cpu mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.5 gt-482xx base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.6 cpu interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.7 cpu interface priorit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 16.8 memor y endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17. sdram interface ........................................................................................................ 80 17.1 dram confi g uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17.2 dram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18. re g ister tables .......................................................................................................... 81 18.1 re g ister description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.2 port mib counters ( 14 blocks ) , offset ( start ) : 0x600, 0xa00, 0xe00, 0x1200 . . . . . . . 107 19. gt-482xx pinout differences .................................................................................. 112 19.1 pinout differences between GT-48207, gt-48208, and gt-48212 devices . . . . . . . . 112 19.2 usin g a gt-48212 in a gt-48208/7 socket: disablin g unused ethernet ports . . . . . . 112 19.3 usin g a gt-48212 or gt-48208 in a GT-48207 socket: disablin g unused cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12 19.4 cclk in an unmana g ed s y stem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 20. gt-482xx pinout tables, 208-pqfp ....................................................................... 114 21. dc characteristics - preliminary/subject to change ) .......................... 120 21.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22. ac timin g - target/subject to change....................................................... 122 23. packa g in g ................................................................................................................. 127 24. document histor y .................................................................................................... 129 appendix a .................................................................................................................... ... 135
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 6 revision 1.2 list of figures fi g ure 1: lo g ic s y mbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 fi g ure 2: block dia g ram of the gt-48212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 fi g ure 3: gt-482xx buffers and queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 fi g ure 4: mii transmit si g nal timin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 fi g ure 5: mmii receive si g nal timin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 fi g ure 6: mdio output dela y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fi g ure 7: re q uired mdio setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fi g ure 8: expansion mii wirin g dia g ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 fi g ure 9: example of serial link status indicator of port 1 link fail. . . . . . . . . . . . . . . . . . . . . . . . . 47 fi g ure 10: primar y status led timin g ( one blink ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 fi g ure 11: primar y status led timin g ( two blinks ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 fi g ure 12: serial led interface timin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 fi g ure 13: i960 write sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 fi g ure 14: i960 write burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 fi g ure 15: i960 read sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 fi g ure 16: i960 read burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 fi g ure 17: coldfire 5202 write sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 fi g ure 18: coldfire 5202 write burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 fi g ure 19: coldfire 5202 read sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 fi g ure 20: coldfire 5202 read burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 fi g ure 21: r3041 write sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 fi g ure 22: r3041 read sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 fi g ure 23: r3041 read burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 fi g ure 24: gt write sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 fi g ure 25: gt write burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 fi g ure 26: gt read sin g le lon g word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 fi g ure 27: gt read burst of four lon g words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 fi g ure 28: serial clock waveform ( sclk ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 fi g ure 29: output dela y from risin g ed g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 fi g ure 30: input setup and hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 fi g ure 31: output dela y from clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 fi g ure 32: output float and drive dela y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 fi g ure 33: 208 lead pqfp packa g e outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 7 list of tables table 1: pinout differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2: pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3: terminolo gy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4: gt-482xx dram address mappin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5: address table entr y format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6: address table entr y field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7: forwardin g of unicast destination address packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8: forwardin g of multicast destination address packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9: priorit y queuin g options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10: smi bit stream format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 11: enablin g /disablin g ports of the gt-482xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 12: spannin g tree enable bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 13: led si g nals available. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 14: led si g nals for mode0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 15: led si g nals for mode1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 16: reset pin strappin g options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 17: gt-482xx cpu support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 18: cpu interface pin mappin g s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 19: cpu mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 20: burst size for different cpu modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 21: re g ister map table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 22: base address, offset: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 23: global control, offset: 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 24: status re g ister, offset: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 25: sniffer and a g in g timer, offset: 0x0c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 26: serial parameters 10 re g ister, offset: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 27: serial parameters 100 re g ister, offset: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 28: watchdo g and tx threshold re g ister, offset: 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 29: interrupt cause, offset: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 30: interrupt mask, offset: 0x1c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 31: cpu tx hi g h desc1 - packet descriptor, offset 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 32: cpu tx hi g h desc2 - packet descriptor, offset 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 33: cpu tx hi g h desc1 - new address, offset 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 34: cpu tx hi g h desc2 - new address, offset 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 35: cpu el free re q , offset: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 36: cpu empt y buffer, offset: 0x34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 37: cpu en q ueue1, offset: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 38: cpu en q ueue2, offset: 0x3c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 39: cpu new address1, offset: 0x40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 40: cpu new address2, offset: 0x44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 41: cpu new address3, offset: 0x48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 42: cpu quer y , offset: 0x4c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 43: smi re g ister, offset: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 44: 802.1q ethert y pe re g ister, offset: 0x54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 45: general purpose re g ister1, offset: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 46: general purpose re g ister2, offset: 0x5c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 47: rx_10 threshold, offset: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
gt-482xx advanced switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 8 revision 1.2 table 48: rx_100 threshold, offset: 0x64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 49: cpu threshold, offset: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 50: led override, offset: 0x6c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 51: flow control source address low, offset: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 52: flow control source address hi g h, offset: 0x74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 53: cpu time out re g ister, offset: 0x7c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 54: dram confi g uration, offset: 0x1448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 55: dram parameters, offset: 0x144c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 56: sdram operation, offset: 0x1474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 table 57: address decode, offset: 0x147c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 table 58: port control ( 10m ports ) , offset: 0x400-0x40c, 0x800 - 0x80c, 0xc00 - 0xc0c . . . . . . 102 table 59: port control 12 ( 100m ports ) , offset: 0x1000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 60: port control 13 ( 100m ports ) , offset: 0x1004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 61: ease re g ister, offset: 0x410-0x41c, 0x810-0x81c,0xc10-0xc1c,0x1008-0x100c . . 107 table 62: definitions used in counter descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 63: port mib counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 64: pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 65: gt-48212 pinout table ( sorted b y pin number ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 66: gt-48208 pinout table ( sorted b y pin number ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 67: GT-48207 pinout table ( sorted b y pin number ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 68: absolute maximum ratin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 69: recommended operatin g conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 70: dc electrical characteristics over operatin g ran g e . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 71: 208 pqfp thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 72: cpu interface timin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 73: switch en g ine interface timin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 122 table 74: mii, led and mdc/mdio timin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 75: serial clock timin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 76: 208 pqfp packa g e dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 77: document histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 9 note: this document applies to all the galaxy gt-482xx devices. all of the information is relevant specifically for the gt-48212 device (12 ether- net ports and two fast ethernet ports). however, all of the functional descriptions are also relevant for all gt-482xx devices. the specific deviations and differences between the devices are described in sec- tion "differences between the gt-48212, gt-48208 and GT-48207" on page 12. 1. g eneral d escription the gt-482xx is a high-performance, low-cost, switched ethernet controller for 10+10/100base-x that provides packet switching functions between 12 or 8 10mbps and two 10/100mbps ports. switch expansion is possible by using one of the 100basex ports working with a separate oscillator. switch expansion can reach up to 60mhz clock frequency to achieve up to 240mbps full duplex bandwidth. the gt-482xx can be used in both managed and unmanaged configurations. the basic operation of the gt-482xx is quite simple. the gt-482xx receives incoming packets from the ethernet or fast ethernet wire, searches in the address table for the destination mac address and then forwards the packet to the appropriate port. if the destination address is not found, the gt-482xx treats the packet as a multi- cast packet. the gt-482xx optionally forwards the packets to specified ports (or all ports in the vlan, if enabled) and optionally to the cpu. the gt-482xx automatically learns the port number of attached network devices by examining the source mac address of all incoming packets. if the source address is not found in the gt-482xx address table, the device adds it to the table indicating on which port the address resides. the gt-482xx then notifies the cpu of the new address via a new_address message and an interrupt. 1.1 fast ethernet ports the gt-482xx integrates two fast ethernet ports. each port works at 10/100mbps (half duplex) or 20/200mbps (full duplex). two media independent interfaces (mii) are provided for glueless connection to off-the-shelf phy chips. full auto-negotiation for both managed and unmanaged switches is supported. one of the fast ethernet ports can be used for switch expansion. in this mode, it can operate at 60mhz clock fre- quency to achieve up to 480mbps full-duplex bandwidth. no special messages other than the regular ethernet packets are passed between two galaxy devices when connected with an expansion port. management cpu treats two devices as separate devices which cannot share learning information. however, the cpu can control the learning (section 6.4.1 "port-based vlan support" on page 28), and vlans can be created by the cpu across the two devices so that the same vlan can share ports on different devices. the gt-482xx incorporates full mii management support. the mdc/mdio pins are directly controlled by the cpu (and the auto-negotiation state machine, when enabled.) 1.2 ethernet ports the gt-482xx integrates 12 or 8 10mbps ethernet ports. each port works at 10mbps (half duplex) or 20mbps (full duplex) and includes the media access control (mac), manchester encoder/decoder, link integrity logic, and a led interface. the gt-482xx ethernet ports are compliant with both the 802.3 and ethernet specifications. each port contains three pins allowing direct interface with the amd quiet (see url: www.amd.com) or the tamarack tc3001 (see url: www.tmi.com.tw) digital filters. link indication from the phy is serially shifted into the gt-482xx on the link- status pins.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 10 revision 1.2 port #0 includes five pins (txen and link status are added) allowing interface to aui, coax, or fiber-optic media. 1.3 flow control and back pressure ieee standard 802.3x flow control (for full duplex) and proprietary back pressure (for half duplex) are supported on both the 100mbps and 10mbps ports. back pressure or flow control is activated when the port or device buffer budget is almost exhausted. 1.4 cpu interface the gt-482xx provides a simple interface for low-cost 32-bit bus processors operating at a 16-50mhz clock rate. the gt-482xx provides glueless interface to the following processors: ? idt 3041 ? mips 64-bit cpus (via the galileo gt-64010a, gt-64011/14 and gt-64120 components) ? motorola coldfire cpus (small amount of glue logic required for demuxed bus versions) ? intel i960 ? jx and i960 ? rx ? other cpus may be attached to the gt-482xx via a pci bus through the gt-64111 pci bridge/bridge memory controller available from galileo in addition, the gt-482xx provides interface to the following processors requiring a minimum amount of glue logic: ? 80486 and derivatives ?i960 ? cx and i960 ? hx processors ? powerpc 401/403 family the cpu performs management functions such as: ? snmp and rmon ? vlan programming ? ip multicast session initiation ? spanning tree bdpu processing ? packet trapping/transmission/reception ? address table access and query. ? layer 3 routing note: a cpu is not required in unmanaged gt-482xx configurations. 1.5 s y nchronous gram/dram interface the gt-482xx interfaces directly to 1 or 4 mbytes of synchronous graphics ram (sgram) or standard sdram. the dram is used to store the incoming/outgoing packets as well as the address table and other device data structures. the interface to the sgram is glueless; all signals needed to control the memory are provided. the gt-482xxs sgram configurations are: ? 1 mbyte (one 256k x 32 device): address table contains up to 2k addresses, 512 rx buffers. ? 4 mbyte (two 1mb x 16 device): address table contains up to 8k addresses, 2048 rx buffers. 1.6 address reco g nition the gt-482xx can recognize up to 8192 (2,024 in 1mbyte configuration) different unicast mac addresses and unlimited multicast/broadcast mac addresses. an intelligent address recognition mechanism enables filtering and forwarding packets at full fast ethernet wire speed. hardware address aging and static address support is also included. the gt-482xx provides an address self-learning mechanism. each device has a private addresstable located in its dram array. as the gt-482xx learns new addresses, it updates the cpu (if present) by sending a new_address message.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 11 the gt-482xx performs unicast address aging on its address table. this can be done automatically or when trig- gered by a cpu request. see section 6.7 "address aging" on page 30 1.7 ip multicast and vlan support when a management cpu is present, the gt-482xx traps igmp packets over ethernet/802.3 (on ipv4 and partial ipv6) and passes these to the cpu. the cpu may then program the port-mask (added to each entry in the address table) and the gt-482xx will lookup the multicast and the broadcast entries in the table and forward them according to the port-mask. in addition, the cpu can program the port masks for source addresses. the gt-482xx forwards the multicast and broadcast packets according to the source address port masks only if the multicast address is not present in the address table. for unicast packets, the gt-482xx checks that the source port appeared in the destination address port-mask bit and forwards the packet only if this bit is set. see also section 6.4 "locked port" on page 27. when unmanaged, the gt-482xx treats multicast packets as broadcast, and passes them to all ports, except for the source port. 1.8 priorit y queuein g each port, including the cpu has two transmit queues for high and low priority. the gt-482xx inserts the packet to the high priority queue if one of the following conditions occur: ? priority bit in the source port control register is set ? priority bit in the address table is set for the destination address ? priority bit in the address table is set for the source address ? the incoming packet contains a 802.1q tag and the most significant bit of the quality of service field in the tag is set. the cpu is able to force the priority regardless of the result of the above conditions. this is done by setting the forcepri bit in the port control register. when forcepri is set, the priority is defined only by the priority bit in the source port control register. in addition to the above conditions, all igmp, bpdu, ease sampled packets and new_address messages are entered into the cpu high-priority queue. all unknown (both unicast and multicast) and broadcast packets are entered into the low-priority cpu queue. 1.9 network mana g ement features the gt-482xx provides comprehensive management capabilities enabling the switch oem to implement a wide range of network management features. for oems offering rmon capability, the gt-482xx provides per-port statistic counters to implement the first four groups of rmon. the gt-482xx includes a unique packet sampling capability invented by the hewlett-packard company called hp-ease (embedded advanced sampling environment.) each port has the ability to take snapshots of packet data at programmable intervals. these samples are forwarded to the management cpu for processing. the sam- ples can be used to implement hp-ease compatible messages for openview environments, or to create custom management information bases such as statistical rmon. since packets are sampled using this technology, less local processing is required over standard rmon implementations. the source addresses of packet errors are also sent to the cpu allowing the switch oem to support error counters in rmon host and matrix groups. the gt-482xx includes hardware assistance for bridge-spanning tree algorithm and full hardware support for address aging.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 12 revision 1.2 1.10 differences between the gt-48212, gt-48208 and GT-48207 the differences between the three galaxy devices are summarized in table 1. table 1: pinout differences galaxy device functions not implemented pins deleted note gt-48212 n/a n/a baseline pinout gt-48208 ethernet ports 1, 5, 7 and 11 all pins related to these ports to use a gt-48212 in a gt-48208 socket, the four unused ethernet ports must be properly disabled. GT-48207 ethernet ports 1, 5, 7 and 11 management cpu interface all pins related to the these ethernet ports and the cpu interface to use a gt-48212 in a GT-48207 socket, the four unused ethernet ports and the cpu interface must be properly disabled.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 13 2. p inout figure 1: logic symbol rst* cclk w/r* blast* ad[31:0] ddata[31:0] (1) ras* (1) cas* (1) we* (1) gt-48212 ads* dram 10mbit int* interface leddata ledstb (1) ledclk miscellaneous interface cpu endev* scan* tristate* sclk rxde[11:0] txde[11:0] (2) interface led interface txclk[1:0] txd0[3:0] col[1:0] rxd0[3:0] rxer[1:0] rxclk[1:0] rxdv[1:0] crs[1:0] txd1[3:0] rxd1[3:0] txen[1:0] 100mbit interface limit4 mdc mdio cole/gp[11:0] ready* dqm (1) serlinkstatus txene[0] (1) daddr[11:0] (1) aclk cs* linkstatus[0] rdcen*/burstaddr[0] burstaddr[2:1] (1) - pins sampled at reset to establish the gt-482xx parameters (2) - pins sampled at reset to establish duplex mode in the 10mbps ports
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 14 revision 1.2 2.1 pin functions and assi g nment table 2: pin functions symbol type description cpu interface rst* i reset : active low. resets the gt-482xx to its initial state. this signal must be asserted for at least 10 mii clock cycles. upon reset deassertion, the gt- 482xx clears the internal empty list and the address table. aclk i internal clock: this clock provides the timing for the gt-482xx internal units. all units, except for the serial interface and the cpu interface, use this clock. this clock can vary between cclk and 66mhz. aclk is also used to clock the synchronous dram. aclk frequency must be no higher than 4x cclk frequency. cclk i cpu clock: this clock provides the timing for the gt-482xx cpu interface. the clock can vary between 16mhz to 50mhz. in unmanaged switch opera- tion, cclk should be tied to the 25mhz 100mbit phy clock. cclk frequency must not be lower than 25% of aclk frequency, and not higher than total aclk frequency. ad[31:0] i/o address data: 32-bit multiplexed cpu address and data lines. during the first clock of the transaction, ad<31:2> contains a physical word address (30 bits). during subsequent clock cycles, ad<31:0> contains data. blast* i last in burst: indicates the last word in the burst. the maximum burst size is 8 words. blast* has alternate meanings depending on cpu mode. ready* o ready: indicates that ad[31:0] lines contain valid data. ready* has alter- nate meanings depending on cpu mode. this output pin features an open- collector driver and should be tied as wired-or in multiple gt-482xx designs. ads* i address strobe: indicates that ad[31:0] holds addresses (when deas- serted it holds data). ads* has alternate meanings depending on cpu mode. w/r* i write read: indicates write/read transaction. the polarity of this pin is pro- grammable depending on cpu mode. int* o interrupt: interrupt request line. int* is asserted by the gt-482xx when one (or more) of the unmasked bits in the interrupt cause registers are set. burstaddr[2:1] i burstaddr: in 3041 mode, contains bits [3:2] of the physical-byte address. in 64010/11 mode, contains bits [2:1] of the address. (see table 16, reset pin strapping options, on page 66.) rdcen*/burstaddr[0] i/o rdcen*/burstaddr: read buffer clock enable / burst address - in 3041 mode, this output pin indicates to the 3041 that the gt-482xx placed valid data on the ad bus. in 64010/11 mode, contains bit [0] of the address. when programmed to be an output, this pin features an open-collector driver and should be tied as wired-or in multiple gt-482xx designs. dram interface
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 15 dqm i/o data output mask: in normal operation, used in read and write cycles to dram. during reset, this pin is sampled by the gt-48212 to indicate the dram size.the gt-482xx always accesses 32-bit values and does not require a separate dqm for each byte. (see table 16, reset pin strapping options, on page 66.) daddr[11:0] i/o dram address: in normal operation, addr lines contains the dram address and bank selection. during reset, pins <11:0> are sampled by the gt-48212. (see table 16, reset pin strapping options, on page 66.) ras* i/o row address strobe: in normal operation, indicates the row address. during reset, this pin in conjunction with cas* and we* indicate the cpu type. (see table 19, cpu mode selection, on page 70.) cas* i/o column address strobe: in normal operation indicates the column address. during reset, this pin in conjunction with ras* and we* indicates the cpu type. (see table 19, cpu mode selection, on page 70.) cs* o chip select: dram chip select. indicates the dram chip select. we* i/o write enable: in normal operation indicates dram write transaction. during reset, this pin in conjunction with ras* and cas* indicates the cpu type. (see table 19, cpu mode selection, on page 70.) ddata[31:0] also used for configu- ration parameters i/o dram data/gt-482xx parameters: multiplexed 32-bit sgram data bus and the gt-482xx parameters. in normal operation ddata[31:0] connect directly to the data input/output pins of the sgdram devices. during reset, some of these pins are sampled by the gt-482xx. (see table 16, reset pin strapping options, on page 66). 10mbps interface txde[11:0] io transmit data (ethernet) / duplex mode . in normal operation carries the transmit data for the 10mbps ports. during reset, these pins are sampled by the gt-482xx to indicate the duplex mode. (see table 16, reset pin strapping options, on page 66). rxde[11:0] i receive data (ethernet): this pin carries the receive data for the 10mbps ports cole/gp[11:0] i collision (ethernet)/general purpose pins: collision detect in aui mode. in 10base-t or 10base-fl these pins are used as general purpose pins. they are sampled or driven according to the general purpose register val- ues. these pins are gp input pins by default, therefore, in 10baset and 10basef modes, these pins should be pulled high or low through a 4.7k ohm resistor. txen[0] io transmit enable: in normal operation indicates that the packet is being transmitted on port 0. during reset, this pin is sampled by the gt-482xx to indicate aui type. (see table 16, reset pin strapping options, on page 66.) sclk i serial clock: 80mhz clock. this clock is used to recover the receive data and to generate the transmit clock for the 10mbps ports. table 2: pin functions (continued) symbol type description
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 16 revision 1.2 serlinkstatus i serial link status indication : this pin is used to serially shift the link sta- tus of ports 1 to 11 from the external phy. ledclk and ledstb are used to clock and strobe the data (assertion of ledstb indicates the beginning of the link data stream). serlinkstatus pin is sampled at the rising edge of ledclk. it should be driven at the falling edge of the ledclk. polarity: high serlinkstatus: link is good low serlinkstatus: link fail. (see figure 9: example of serial link status indicator of port 1 link fail on page 47). linkstatus[0] i link status indication : this pin is used to indicate the link status of port 0 from the external phy. polarity: high linkstatus[0]: link is good low linkstatus[0]: link fail. (see figure 9: example of serial link status indicator of port 1 link fail on page 47). 10/100mbps interface (mii) txen[1:0] o transmit enable: active high. this output indicates that the packet is being transmitted. txen is synchronous to txclk. txclk[1:0] i transmit clock: provides the timing reference for the transfer of txen, txd signals. txclk frequency is one fourth of the data rate (25 mhz for 100mbps, 2.5 mhz for 10mbps, 60mhz for 240mbps). txclk nominal frequency should match the nominal frequency of rxclk for the same port. txd0[3:0] o transmit data 0: outputs the port0 transmit data. synchronous to txclk[0]. txd1[3:0] o transmit data 1: outputs the port1 transmit data. synchronous to txclk[1]. col[1:0] i collision detect: active high. indicates a collision has been detected on the wire. this input is ignored in full-duplex mode. col is not synchronous to any clock. rxd0[3:0] i receive data 0: port 0 receive data. synchronous to rxclk[0]. rxd1[3:0] i receive data 1: port 1 receive data. synchronous to rxclk[1]. rxer[1:0] i receive error . active high. indicates that an error was detected in the received frame. this input is ignored when rxdv for the same port is inac- tive. rxclk[1:0] i receive clock . provides the timing reference for the transfer of the rxdv,rxd,rxer signals (per port). operates at either 25 mhz (100mbps), 2.5 mhz (10mbps) or 60mhz (240mbps). the nominal frequency of rxclk (per port) should match the nominal frequency of that ports txclk. rxdv[1:0] i receive data valid: active high. indicates that valid data is present on the rxd lines. synchronous to rxclk. crs[1:0] i carrier sense: active high. indicates that either the transmit or receive medium is non-idle. crs is not synchronous to any clock. table 2: pin functions (continued) symbol type description
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 17 mdc o management data clock: provides the timing reference for the transfer of the mdio signal. this output may be connected to the phy devices of both ports. mdio i/o management data input/output: this bidirectional line is used to transfer control information and status between the phy and the gt-482xx. it con- forms with ieee std 802.3. this signal may be connected to the phy devices of both ports. when not driven by an mii compliant phy, this pin must be connected to a pull-up or pull-down resistor. phy register reads per- formed by the gt-482xx will be decoded as all 1's or all 0's respectively." led interface pins ledstb/ledmode i/o led strobe/led mode: multiplexed led strobe and led mode. in normal operation, envelopes the full-duplex and link-status data stream (bit #0 to bit#27) of a valid data frame on leddata output. during reset, indicates the led mode. (see table 16, reset pin strapping options, on page 66.) ledclk o led clock: 1 mhz clock. this output is used to clock the ledstb and led- data outputs. during reset, ledclk output is tri-stated. leddata o led data: active low. serial data bit stream which contains the led indi- cators per port. the data is shifted out using the ledclk. ledstb is used to mark the first data bit. miscellaneous interface pins endev* i enable device: this pin together with endev bit in the global control regis- ter activate the ports as follows: note : endev* is not synchronous to any clock scan* i scan: this pin together with tristate* indicate the gt-482xx mode of opera- tion as follows: factory test modes are reserved and are not to be used in system. failure to observe this restriction could result in damage to the device. table 2: pin functions (continued) symbol type description endev* endev bit mode 0 x enable 1 0 disable (default) 1 1 enable scan* tristate* mode 1 1 normal operation 0 1 factory test mode (reserved) 1 0 the gt-482xx drives all outputs and i/o pins to high impedance. 0 0 factory test mode (reserved)
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 18 revision 1.2 tristate* i tri-state: this pin together with scan* indicate the gt-482xx mode of oper- ation as described above. limit4 i backoff algorithm: this pin together with limit4 pin in the global control register selects the number of consecutive packet collisions that will occur before the collision counter is reset. when the logical or of this pin and the bit is low, 16 consecutive collisions must occur before the collision counter is reset (802.3 standard). when high, four consecutive collisions must occur before the collision counter is reset (more aggressive.) note : limit4 is not synchronous to any clock. table 2: pin functions (continued) symbol type description
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 19 3. g alaxy f amily o verview the galaxy family of switching devices is designed to provide the lowest cost solutions for desktop and work- group ethernet switching. the galaxy family currently includes the following devices: ? gt-48212 twelve ports of 10basex, two ports of 100basex with management interface ? gt-48208 eight ports of 10basex, two ports of 100basex with management interface ? GT-48207 eight ports of 10basex, two ports of 100basex but without any management capability. the GT-48207 is designed for cost-sensitive hub replacement applications. during the design of the galaxy family, galileo technology had the following goals: ? produce a product yielding the lowest possible system cost. this is evident in the galaxy familys high level of integration and lower overall bill-of-materials. for example, galaxy family devices do not require the external address lookup/vlan engines and phy devices required by other solutions. we have also made it very simple to interface a cpu. ? make it simple for the switch oem to build a modular/flexible product line. the gt-48212, gt- 48208, and GT-48207 all share a common pinout. this allows the oem to build a variety of port densities and management options on the same printed circuit board. this flexibility allows the oem to manage production planning more effectively. ? provide software compatibility to future generations. future generations of galaxy devices that support different port speeds/densities will strive for backwards software compatibility. this allows you to write your management code once, and only modify it as your end-user requirements change. galileo technology will continue to extend the galaxy family to meet future needs for workgroup/desktop lans. the galaxy family uses a store-and-forward switching approach. store-and-forward was chosen for the follow- ing reasons: ? store-and-forward switches allow switching between different speed media (e.g. 10basex and 100basex.) such switches require the large elastic buffers that are provided by the sdram arrays. ? store-and-forward switches improve overall network performance by acting as a network cache, effec- tively buffering packets during periods of heavy congestion. ? store-and-forward switches prevent the forwarding of corrupted packets by analyzing the frame check sequence (fcs) before forwarding to the destination port. 3.1 basic operation the basic operation of the gt-482xx is quite simple. the gt-482xx receives incoming packets from the ethernet wire, searches in the address table for the destination mac address and then forwards the packet to the appro- priate port. the destination port can either be local (one of the gt-482xxs ports) or in a different gt-482xx device that is connected via the fast mii expansion bus. if the destination address is not found, the gt-482xx treats the packet as a multicast packet and forwards the packet to all ports of all the devices in the system specified to for- ward unknown packets. the gt-482xx automatically learns the port number of attached network devices by examining the source mac address of all incoming packets. if the source address is not found in the gt-482xxs address table, the device adds it to the table (indicating on which port the address resides). the gt-482xx then notifies the cpu (if present) of the new address via a new_address message. 3.2 address learnin g the gt-482xx can learn up to 8k unique mac addresses. addresses are stored in the address table located in the dram. the address table is managed automatically by the gt-482xx (i.e. a new address is automatically added to the address table). the gt-482xxs address learning process is detailed in section 6. "mac address table" on page 26.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 20 revision 1.2 the address table includes information regarding target port, aging status, static/dynamic status, vlan, and flags to force processor intervention. the management cpu has the ability to insert, remove or modify the entries. 3.3 packet bufferin g incoming packets are buffered in the sdram array. these buffers provide elastic storage for transferring data between low-speed and high-speed segments. the gt-482xx automatically manages packet buffers. 3.4 packet forwardin g once an address has been learned and the packet is buffered, it must be forwarded. the packet forwarding mech- anism for the gt-482xx is handled automatically based on the destination address. optionally, the cpu can be involved in unicast packet forwarding decisions by using intervention mode . for more information about interven- tion mode see section 7.5 on page 35. if a cpu is utilized for system management functions, multicast packets are forwarded to the cpu for forwarding decisions. 3.5 terminolo gy it is important to understand the basic terminology used to describe the galaxy family before getting into a detailed description. table 3 explains the terms used throughout this document. table 3: terminology term definition address table the address table is a data structure in the gt-482xxs dram that contains all learned mac addresses, and routing information associated with those addresses. source address the source address (sa) is the mac address from which a received packet was sent. destination address the destination address (da) is the mac address to which a received packet is directed. port number each ethernet port on a galnet device has an associated port number. the gal- net device associates port numbers with the mac addresses located on those ports.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 21 4. m icroarchitectural o verview the gt-482xx is comprised of the following hardware units: cpu interface the cpu interface includes all interface functions to the cpu bus. it handles all interconnect control signals and executes cpu slave transactions. the cpu interface unit controls the packet transfer between the gt-482xx and the cpu. it includes simple registers for passing messages to/from the cpu. the gt-482xx is always a slave on the cpu interface. sdram interface includes all the interface functions to 1 or 4mbyte sgram or sdram. it generates the con- trol signals and drives the address/data lines. switching core performs the switching functions between the 12 or 8 10mbit ports and the two 100mbit ports and the cpu. 10mbit port unit there are three 10mbit port units in the gt-48212 (two in the GT-48207 and gt-48208). each handles four 10mbit ports and consists of dma, four 64x32-bit word fifos (one for each port), counters and serial interface blocks. packets are transferred between the dram interface and the ethernet 10mbit serial interface. it uses the gt-482xx rxm,txm and sia with the addition of the mac-control block that performs igmp trapping and flow control. 100mbit port unit there is one such unit. each handles two 100mbit ports and consists of dma, two 128x32-bit fifos, counters and serial blocks. packets are transferred between the dram interface and the ethernet 10mbit serial interfaces. it uses the gt-482xx rxm, txm and mii with the addi- tion of the mac-control block that performs igmp trapping and flow control.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 22 revision 1.2 figure 2: block diagram of the gt-48212 cpu interface ci_unit switch control sc_unit sdram interface arbiter empt y list address desc . ctl. leds int. memor y mac10 txm10 par. rxm10 par. cnt 10 dma10 fifo10 mac10 txm10 par. rxm10 par. cnt 10 dma10 fifo10 mac100 txm100 par. rxm100 par. cnt dma100 fifo 100 100 pt_unit pt_unit po_unit mac10 txm10 par. rxm10 par. cnt 10 dma10 fifo10 pt_unit test lookup
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 23 5. b uffers and q ueues the gt-482xx incorporates 30 transmit queues for the 12 or 8 ethernet ports, two fast ethernet ports and the cpu bus port. in each port there are two queues, one for high and one for low priority. the gt-482xx also con- tains a common receive buffer area. the receive buffers are allocated to the receive ports and the cpu. the gt- 482xx incorporates a simple mechanism to prevent head-of-line blocking (see section 5.2 "head-of-line block- ing" on page 25). the receive buffers as well as the transmit queues are located in the dram with the address table. see table 4 on page 24 for dram address mapping in the gt-482xx. the gt-482xx data structure has the following components: ? receive buffer - a common receive buffer area for all ports. the buffer is divided into 512 or 2048 blocks (depending on the dram size) of 1.5kbytes (1536 bytes) each. each block contains the entire packet. ? rx empty list - a list of 512 or 2048 bits. each bit contains the status of its appropriate receive block in the dram (empty or occupied). ? tx descriptors - a set of 30 transmit descriptor rings. each ring contains 512 or 2048 descriptors. the descriptor size is one 32-bit word and contains the block address divided by 0x600 (1.5k), the byte count and the packet type (multicast or unicast). ? read/write pointers - 30 pairs of pointers to the transmit descriptors.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 24 revision 1.2 figure 3: gt-482xx buffers and queues 5.1 rx buffer threshold pro g rammin g the number of receive buffers allocated to each port of the gt-482xx is controlled by the rxbufthr fields in the rx buffer threshold registers. the default value is 32 (10mbps) or 64 (100mbps) buffers per port for 1mb dram and 64 (10mbps) or 592 (100mbps) buffers per port for 4mb dram. if the buffer threshold is disabled by clearing the table 4: gt-482xx dram address mapping memory description 1mbyte 4mbyte rx buffers 512 buffers for 1mbyte 2048 buffers for 4 mbyte 0x00000 - 0xbffff 0x00000 - 0x2fffff multicast indicators 4 bytes per buffer 0xc0000 - 0xc07ff 0x300000 - 0x301fff tx descriptors 28 descriptor queues 0xc0800 - 0xce7ff 0x302000 - 0x339fff cpu descriptors 2 descriptor queues 0xce800 - 0xd6800 0x33a000 - 0x341fff reserved - 0xd0800 - 0xe7fff 0x342000 - 0x39ffff address table 2k addresses for 1mbyte 8k addresses for 4mbyte 0xe8000 - 0xfffff 0x3a0000 - 0x3fffff read pointer write pointer 21 byte count blk addr 10 9 0 frame #0 frame #1 frame #2 receive buffer tx descriptors: 512/2048 x 30 rx empty list dram gt-48212 m/u 20 frame #n
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 25 bufthren bit in the global control register or the daddr[10] pin is held low during reset, the gt-482xx dynami- cally allocates the buffers to the 14 ethernet ports and the cpu. therefore, there are no limits on each buffers allocation. the rx buffer threshold value can be used for performance tuning during development. for more details about the rx threshold register see table 47 on page 99, table 48 on page 99, and table 49 on page 100. if a received packet overflows the receive buffer allowance, the packet is discarded and the dropped packets counter incremented. 5.2 head-of-line blockin g the gt-482xx incorporates a simple mechanism to prevent head-of-line (hol) blocking. this is done by passing an indication from the transmit queues to the buffer allocation machine. a packet destined to a transmit port will be discarded if the following conditions are met: ? the transmit queue of destination port exceeds a programmable threshold (as defined in the txthr field in the tx threshold register) ? number of buffers allocated to this source port is equal to or greater than the hollimit value (in rx threshold registers). hol prevention is enabled only when the gt-482xx is in fixed rx buffer mode (bufthren = 1).
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 26 revision 1.2 6. mac a ddress t able the gt-482xxs address table resides in the local dram array. table 5 and table 6 show the address table structure. the address table structure occupies approximately 320kbytes (in 4mbyte configuration) or 80kbtytes in 1mbyte configuration) and is entirely controlled and initialized by the gt-482xx. following reset, the gt- 482xx initializes the address table by invalidating all entries. modifications to the address table are normally made through new_address message requests by the cpu. the address table can be accessed directly, however, this mode is not recommended. contact galileo technology if your application requires direct address table access. 6.1 forwardin g mask the forwarding mask (forw<14:0>) controls forwarding options in managed systems. each bit in the mask corre- sponds to a specific port in the gt-482xx device. port 0 corresponds to bit 0 (least significant bit), port 13 corre- sponds to bit 13. bit 14 corresponds to the cpu port (if present). when the gt-482xx performs new address learning, the forw[14:0] bits are set to 0x7fff (all 1's). the forw<14:0> operation is described in table 6. 6.2 port number the port number field in the address table corresponds to the port on which a specific address was detected (learned). port 0 = 0x0 in this field, cpu port (port 14) corresponds to 0xe. table 5: address table entry format forw<14:0> mac<47:0> is id mul st port #pspdaskv 15 48 11 1 1 4 11111 number of bits in each field is shown above. table 6: address table entry field description bit general description v valid - indicates that the entry is valid 1 - valid 0 - not valid sk skip - skip this entry. it is being used to delete an entry 1 - skip this entry 0 - dont skip this entry a aging - this bit is used in the address aging process. - cleared by the gt-482xx upon receiving a packet from this station. - set by the gt-482xx during aging processing (for more information see the aging algorithm in section 6.7) pd destination address effect on priority. 1 - enqueue to high priority queue.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 27 6.3 address learnin g process the gt-482xx has a self-learning mechanism for learning the mac addresses of attached ethernet and fast ethernet devices in real time. the gt-482xx searches for the source address (sa) of an incoming packet in the address table and acts as follows: 1. if the sa was not found in the table (a new address) at the end of the packet, the gt-482xx updates its address table. the gt-482xx can also send a new_address message to the cpu (if present), and if programmed to do so. 2. if the sa was found, the gt-482xx compares the port number to the existing port number. if they are dif- ferent and the static bit is clear, it updates the entry with the new information (and optionally notifies the cpu). else, no action is taken. 3. when a source address exists in the table the aging bit is set. when the static bit in the address table is set, the gt-482xx does not modify the entry. when both the static and multiple bits are set, the gt-482xx does not modify the entry and forwards the packet as multicast. it forwards the packet according to the forw bits of the destination address. when two galaxy devices managed by the same cpu are configured, the cpu may receive new address infor- mation from both devices, since each device reports learning on its own port. the first learning is on the network port, and the second learning is on the expansion port. 6.4 locked port the cpu has the ability to lock one or more ethernet/fast ethernet ports. this is done by setting the lockport bit in the port control register. in this mode, the gt-482xx does not learn any new addresses received from this port. ps source address effect on priority. 1 - enqueue to high priority queue. port# port number for this mac address. st static 1- the entry is static. the port# can not be modified 0 - the entry can be modified mul multiple - meaning when bit st is set 1 - forward this packet as multicast destination address entry. 0 - forward this packet only to the destination port. id forward to cpu only when it is destination addresses 1 - forward packet to the cpu when address is destination. 0 - no effect is forward to cpu only when it is source addresses 1 - forward packet to the cpu when address is source. 0 - no effect mac 48 bit of mac address. forw forward the packet also to the following ports/cpu (bit mask). table 6: address table entry field description (continued) bit general description
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 28 revision 1.2 the gt-482xx does not modify the address table and sends a new_address message only to the cpu. the gt- 482xx decides whether to discard or forward the packet based on the dislock bit in the global control register. if this bit is reset, then packets received from new sa on a locked port are discarded. the cpu can also prevent sending unknown packets to this port. this is done by setting the forunk bit in the port control register. note : in locked port mode, a station that moved to a new port receives a new address, therefore, packets com- ing from the station that moved are discarded until the cpu reprograms the gt-482xx with the new port number. 6.4.1 port-based vlan support the user can implement port-based vlans using the gt-482xx for both one chip and two chip configurations using the locked-port feature: ? the cpu programs all ports as locked ports. ? the gt-482xx sends new_address messages only to the cpu. ? the cpu sends the forward mask for each source address (that is legal for that port) back to the gt- 482xx. vlans that span ports in two-chip gt-482xx configurations can be defined. since all ports are locked ports, the gt-482xx checks the forwarding legality from source to destination, and assures security. the user can define port-based vlans with common ports and still maintain security. for more information see section 6.6 "address recognition". the user can optionally define the forwarding masks to represent port-based vlans that do not share ports. 6.5 address entr y update and quer y from cpu this interface is used to receive new_address messages from the cpu. the messages can be new address table entries, updates to existing ones, or queries from the cpu. the query from the cpu is a mechanism in which the cpu can read the data from the address table. the gt-482xx responds by searching the address table for the requested mac address, and returns the result to the cpu in the query register. to perform these tasks the gt-482xx maintains three 32-bit registers called na_from_cpu registers. these three 32-bit registers are written by the cpu to update the gt-482xx with a new/modified address entry, or with a query message cpu initiates a query by sending a new_address message with a query bit set. the gt-482xx responds by searching the address table for the entry and places the address information in the query register. the gt- 482xx then generates an interrupt. 6.6 address reco g nition the gt-482xx forwards incoming packets to their appropriate port(s) according to the destination address (da), and source address (sa) in the address table and the programming modes of each ports port control register (pcr) and global control register (gcr) as follows: 1. the following principles are always valid: ? a packet is not forwarded to any port if the port is disabled, link is down, or in span-mode (except bpdu to a span port). ? a packet is never forwarded on the port from which it was received. ? if gcr.dispktlock =0 then any received packet (unicast or multicast) from a port that has pcr.locked=1, with a new sa (or sa that moved to this port), the packet is discarded, regardless of the da. 2. otherwise, the forwarding of a packet received on any of the 14 ports can be unicast or multicast desti- nation addresses as follows: 2.1 unicast destination address:
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 29 if (sa has is=1 or the da has id=1 (in the address table entries). forward only to cpu (as inter- vention) else forward as shown in table 7 note: "sa found" represents a valid source address table entry found in the addresstable. "x" represents "dont care" 2.2 multicast destination address: if the packet is bpdu, see section 11.3 "spanning tree (bpdu) support" on page 50. if the packet is an igmp packet, see section 7.6 "igmp packet support" on page 35. if da=ffffffff and pcr.filbroad=1 in the recieving port, the packet is discarded. if da=ffffffff and pcr.filbroad=0 and pcr.forwbroadcpu=1, the packet is forwarded only to cpu. if (sa has is=1 or the da (multicast) has id=1 (in the address table entries) or gcr.forwmulti- cpu=1, forward only to cpu (as intervention) else forward as shown in table 8. table 7: forwarding of unicast destination address packet sa found ? da found? das forward- mask includes receive port? da is static & multiple forward to... xyes1 noda x yes 0 x packet dropped yes no - - all ports in sa that have pcr.forw_unk=0 (and also to cpu if it is in the forward mask and gcr.forw_unk=1) no no - - all ports that have pcr.forw_unk=0, and also cpu if gcr.forw_unk=1) yes yes 1 yes sa bitwise and da no yes 1 yes da table 8: forwarding of multicast destination address packet sa found? multica st da found? das forward- mask includes receive port? forward to... yes yes 1 sa bitwise and da no yes 1 da
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 30 revision 1.2 note: "sa found" represents a valid source address table entry found in the addresstable. "x" represents "dont care" note : the algorithms detailed in this section do not describe the handling of incoming pause packets (for 802.3x flow-control). these packets are never forwarded to other ports, once they are recognized as pause packets. if flow control is disabled, these packets are not recognized as pause packets, and treated as regular multicast packets. 6.7 address a g in g the gt-482xx performs unicast address aging on its address table. aging can be done automatically or when triggered by a cpu request. once a mac address has been aged or removed from the address table, packets with this mac address as its destination address are broadcasted to all ports. there are three aging modes pro- grammed using bits [3:2] in the global control register as follows: ? gcr[3:2] = 00 no hardware aging support. ? gcr[3:2] = 01 automatic aging support - the gt-482xx includes an internal aging timer. when the timer expires, the gt-482xx scans the address table and ages out (removes) all addresses for which the aging bit is clear. ? gcr[3:2] = 10 trigger mode. ? gcr[3:2] = 11 reserved. in automatic aging mode, the gt-482xx automatically sets and clears the aging bit in the address table. static addresses are not aged out. 6.7.1 determining aging time the gt-482xx uses two variables to determine the aging time when aging is enabled: ? the frequency value of aclk ? the aging timer variable, n, bits[14:9] at offset 0x0c. the source address is removed (aged) from the address table if a packet with a learned source address is not received by the switch as follows: [(500/aclk freq) * n] seconds and [(1000/aclk freq) * n] seconds x yes 0 packet dropped yes no - sa no no - all ports (including cpu) table 8: forwarding of multicast destination address packet (continued) sa found? multica st da found? das forward- mask includes receive port? forward to...
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 31 the default value of the aging timer is 30d (0x1e). therefore, if aclk is 50mhz, the default aging time will be 300 to 600 seconds. if aclk is 66mhz, the default aging time will be 227 to 455 seconds. the aging time range is determined by a scan mechanism that scrubs the entire table within [(500/aclk freq) * n] seconds. the age scan pointer looks up all entries within this time range. a given entry can be located anywhere in the address table, therefore, the age scan pointer will look up the same entry twice in no less than [(500/aclk freq) * n] seconds, and no more than [(1000/aclk freq) * n] seconds. 6.7.2 cpu trigger mode when the cpu trigger mode is enabled, the address table is scanned once for every trigger. the time for this scan is [(500/aclk freq) * n] seconds. 6.8 static addresses the gt-482xx provides support for static mac addresses. ieee 802.1d chapter 3.9.1: "static entries may be added to and removed from the filtering database under explicit management control. they are not automatically removed by any time-out mechanism. this means that when an address is selected as static, it is not removed from the address table during aging. during normal address recognition, if an address is static and the port is unlocked, the gt-482xx does not update its address table parameters and does not send a new_address message to the cpu (if the address has changed ports). when the port is locked, the gt-482xx sends the new_address message to the cpu only. 6.9 address reco g nition failure an address recognition cycle can fail when more than 8k addresses have been entered into the address table. in the case of an address recognition failure the packet is treated as unknown and forwarded to all ports. an interrupt is also generated to the cpu (if present). address recognition failures are not fatal and do not require handling. therefore, designers of unmanaged sys- tems need not be concerned with such a failure. when such a failure occurs in managed systems, the address table may be cleaned of old addresses. 6.10 forwardin g priorit y the gt-482xx supports two levels of forwarding priority (high and low) for all 14 transmit ports, and for transmis- sion to the cpu. priority is supported by maintaining two packet queues per port. 6.10.1 priority assignment bpdus, igmp and sampled hp-ease packets are enqueued to high priority. new_address messages to the cpu are also entered into the high priority queue. unknown unicast, unknown multicast and broadcast packets are enqueued to the cpus low priority queue when their reception to the cpu is enabled. known unicast and known multicast packets are enqueued according to the priority mode. the packet is entered to the high priority queue when one of the following conditions are met: ? priority bit in the source port control register is set for the input port ? priority bit in the address table is set for the destination address ? priority bit in the address table is set for the source address ? the incoming packet contains an 802.1q tag and the most significant bit of the quality of service field in the tag is set (priority is greater or equal to 4). the cpu can force the priority regardless of the results of the above conditions by setting forcepri bit in the port control register. when forcepri is set, the priority is defined only by the priority bit in the source port control reg- ister.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 32 revision 1.2 the priority of packets enqueued by the cpu are set by the cpu. 6.10.2 priority throttling the global control register contains a priority weight field that controls the priority of the high priority queue ver- sus the low priority queue. options range from fair round robin (i.e. no difference in priority) to high priority (high priority packets are always forwarded first). there are six priority weights between the highest and lowest extremes as shown in table 9. table 9: priority queuing options priority weight forwarding behavior weight as% h/l 000 one packet transmitted from the high priority queue, and one packet transmitted from the low priority queue 50/50 001 two packets from the high queue, one from the low 66/33 010 four packets from the high queue, one from the low 80/20 011 six from the high queue, one from the low 85.7/14.3 100 eight from the high queue, one from the low 88.8/12.2 101 10 from the high queue, one from the low 90.9/9.1 110 12 from the high queue, one from the low 92.3/7.7 111 all packets from the high queue. 100/0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 33 7. p acket f orwarding this section details the procedures used to forward packets with the following conditions: ? unicast packet to a local port ? multicast packet to local ports and the cpu ? packet destined for the cpu (multicast, or unicast packet from the gt-482xx to the cpu) ? unicast/multicast packet from the cpu to the gt-482xx 7.1 forwardin g a unicast packet to a local port the sequence for forwarding a unicast packet to a local port is as follows: 1. the incoming packet is fed to the rx fifo (there is a 64x32-bit rx fifo for the 10m ports and 128x32- bit rx fifo for the 100m ports) and is transferred to an empty block in the receive buffer area of dram. 2. in parallel, an address recognition cycle is performed for both the da and the sa. the gt-482xx uses the das corresponding port number to queue the packet to the appropriate local port. 3. at the end of an error-free packet transfer, packet information is written to the appropriate ports transmit descriptor. this information includes the byte count and the receive buffer block address which is pointed to by the write pointer. 4. the write pointer of the outgoing ports transmit descriptor is incremented. the gt-482xx transmits whenever the write pointer is not equal to the read pointer. 5. at the end of the packet transmit process, the gt-482xx increments the read pointer and clears the appropriate bit in the empty list. 7.2 forwardin g a multicast packet the gt-482xx forwards multicast packets to all local ports and the cpu using the same mechanism as described for unicast packets. the gt-482xx has the ability to forward multicast packets to a management cpu for inter- vention routing, if desired. 7.3 forwardin g a packet to the cpu systems that utilize a cpu (cpuen of the global control register) can receive packets from the gt-482xx using a simple slave interface. this includes the following packet types: ? unicast packets destined for the cpu (port number in the address table equal to 14d) ? multicast packets ? unknown packets (if set by forwunk bit in the global control register) ? igmp packets ? bpdu messages ? sniffer packets when the cpu is the target sniffer ? ease packets the cpu transmit descriptor queues are used to store the outgoing packets from the gt-482xx ports to the cpu, and to pass new_address messages to the cpu. the gt-482xx does not dma packets to the cpu. the cpu reads the descriptors and then accesses the buffer contents directly from the gt-482xxs sdram. the gt-482xx provides the cpu with one descriptor at a time (in a dedicated, single register). the cpu can then access the packet in the sdram (read/write) and provide an end_of_packet message to the gt-482xx, in a dedicated regis- ter so that the gt-482xx will free the buffer in dram. there are two packet queues (high and low priority). each queue has the following data structure components: ? cpu_tx_hi/low_desc register . these two registers (one for high priority and one for the low-priority queue) are loaded with the next descriptor. each 64-bit register holds the next descriptor, a new_address message or an errored source address to the cpu. when the gt-482xx has a new cpu descriptor, it attempts to write it into one of the cpu_tx_hi/low_desc registers (depending on priority). the new descriptor is written to the register provided that bit 31 of the second word is cleared. bit 31 of
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 34 revision 1.2 the second word (valid bit) is automatically cleared when the cpu reads the register. if this bit is not cleared when the gt-482xx attempts to write, the next descriptor is reloaded when the valid bit is reset. an interrupt is asserted (if not masked) when a new descriptor is successfully written. ? cpu_el_free_req register . this 32-bit register is written by the cpu to signal to the gt-482xx that the buffer can be cleared in the sdram (typically this is done after the cpu has read the packet from the gt-482xx memory). the gt-482xx clears the busy bit in this register when it is ready to receive another command. the cpu reads this register before writing to it to check that it is clear. the sequence for forwarding a unicast packet to the cpu is as follows: 1. the incoming packet is fed to the receive fifo and transferred to an empty block in the dram. 2. in parallel, an address recognition cycle is performed for the sa and the da (unicast or multicast). 3. at the end of a good packet transfer, the packet is forwarded to the cpu tx queue. the packet is for- warded by writing the following information to the tx-descriptor pointed to by the queue producer: type (packet/na), source port#, byte count, buffer address. in addition the relevant bits are set: multicast, uni- cast, broadcast, intervention, unknown, new_address, ease. in the case of multicast/broadcast pack- ets, the gt-482xx sets the multicast indicator bits in the sdram. 4. the cpu tx high/low queue producer index is incremented. when the write pointer is not equal to the read pointer, the gt-482xx checks if the cpu_tx_high/low_desc register can be loaded, if it can be loaded, the descriptor pointed by the read pointer is loaded into the cpu_tx_high/low_desc register and the read pointers incremented. the cpu is then interrupted. 5. the cpu reads the cpu_tx_high/low_desc register. the cpu can read/write to the packet buffer directly. when completed the cpu writes an end_of_packet message to the cpu_el_free_req regis- ter. 6. after getting the end_of_packet message, the gt-482xx clears the multicast indicator bit of the cpu (if it was multicast) and if cleared - resets the appropriate bit in the empty list and decrements the rx_block_counter of the source port. 7. instead of stages (5) and (6) above, the cpu can enqueue the packet for transmission (without copying to another buffer, but after modifying it). this mechanism applies only to unicast packets, or to multicast- packets that were forwarded only to the cpu. this may be useful when the cpu wants to do intervention on traffic and redirect it (after optionally modifying the packet contents), without copying the entire packet to its memory. the source port number written to the cpu enqueue register should be the original source port number and not the cpu (port number 0xe). 7.4 forwardin g a packet from the cpu to the gt-482xx this interface is used to transmit packets from the cpu to the ethernet ports. the cpu requests the next empty buffer, writes to the dram directly, and then requests queueing of a single packet to a port tx queue (equivalent to end_of_packet message in the galnet architecture family). cpu packet transmission is performed with a simple register interface that allows handling one packet enqueue at a time. getting empty buffer addresses and enqueueing packets are two independent mechanisms - for example: the cpu can re-enqueue packets that it received from the gt-482xx for transmission back to port(s) using the same buffer (without getting an empty buffer). also the cpu can take several empty-buffers (one at a time) write to them directly, and enqueue them in arbitrary order. the following registers are used for this process: ? cpu_empty_buffer register . this register is loaded by the gt-482xx with the next el address. the reg- ister is 32-bits and holds el address and valid bit. reading from it signals the gt-482xx that the cpu owns the buffer (resets valid bit). a new el request will be issued automatically to the el block (same format as before), unless cpu_block_counter register reached the allowed maximum. it is the cpus responsibility to release the buffer (the gt-482xx does not record which buffers are owned by the cpu) - this is done when the cpu requests enqueueing packet for transmission. ? enqueue_from_cpu register . this 64-bit register is used by the cpu to request enqueueing a packet to be transmitted over the gt-482xx ports. the cpu writes the end_of_packet message here (in the for-
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 35 mat that the descriptor_control block is expecting). the register holds the information needed to enqueue the packet (as the cpu has already wrote the buffer contents) and a busy-bit in the second word (bit 31). the busy-bit is set by the gt-482xx whenever the cpu writes to the register and reset by the gt-482xx when it is ready to receive a new enqueue request. the cpu is allowed to send a packet to a disabled port. the tx watchdog timer will eventually remove the packet from the tx queue and release its buffer. the recommended structure of an interrupt service routine that handles packets that are forwarded to the cpu is as follows: 1. mask the interrupt for new packets by writing to the interrupt mask register the appropriate value. 2. clear the interrupt cause bit. 3. read cpu_tx_desc1 4. read cpu_tx_desc2 5. read the interrupt_cause register, and see if there is a new packet. if yes then repeat steps (1 )-(4), oth- erwise enable interrupt receiving by clearing the mask register and exit the isr. 7.5 intervention mode intervention mode permits software or hardware intervention in the packet routing decision mechanisms. a packet that is determined to require intervention will be enqueued only to the cpu (overriding the da port#, forw<14:0> fields and vl decisions). this is supported for multicast and for unicast packets and is performed when the cpu has set the sa or the da intervention fields in the address table. 7.6 igmp packet support when global_control[igmp_en]=1, the gt-482xx traps igmp packets that are received on any of its ports using ipv4 and partial ipv6 over ethernet v2 or 802.3 snap encoded (llc is aa-aa-03-00-00-00) and passes them to the cpu. see appendix a on page135 for an illustration of the ethernet packet formats. the cpu can then pro- gram the gt-482xx to efficiently switch/filter ip multicast traffic. the cpu can send the gt-482xx a new_address message containing a multicast-mac entry that will include the correct forwarding mask for this multicast address. the gt-482xx performs the following algorithm on each of its 14 ports when forwarding igmp packets: if ((global_control==1) and (da is multicast or broadcast) and (source is not cpu) and (packet is igmp) then forward packet only to cpu, on high priority queue. packet can be identified as igmp by the following algorithm: (format is ethernet or snap) and (ethertype is ip (0x0800)) and ( (ip version == 4 and protocol ==igmp (0x02)) or (ip version == 6 and payload type == igmp (0x02) ) 7.7 crc generation the gt-482xx includes a crc generator for packets transmitted by the cpu. the crc generator enhances sys- tem performance by implementing the cpu intensive packet fcs calculation in hardware. the crc generation is not required for packets transferred between ports or devices, since the crc is already appended to these pack- ets. crc generation for cpu generated packets is enabled through the encrc bit in the global control register. in addition, the cpu must set the gencrc bit in the enqueue1 register.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 36 revision 1.2 7.8 tx watchdo g timer the gt-482xx includes a transmit watchdog timer for each transmit queue. for 100mbps operation, the default value of the timer is 63msec; the range is between 10.5 to 168msec. for 10mbps operation, the default value of the timer is 630msec and the range is between 105msec to 1680msec. the timer measures the time between the transmission of two consecutive outgoing packets. when the timer expires, the gt-482xx clears the appropriate used blocks and sends an interrupt to the cpu via int*. the transmit watchdog timer prevents transmission problems on one port from blocking traffic to other ports. in managed systems, the timers also provide a mechanism to notify the cpu of a possible system problem. the tx watchdog timer can be externally disabled by holding the diswd* pin low. the default is to leave the tx watchdog timer (diswd* high) enabled.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 37 8. f ast e thernet i nterfaces the gt-482xx interfaces directly to two mii (media independent interface) ports which are compliant with the ieee standard (please see 802.3u fast ethernet standard for detailed interface information and timing parame- ters). each mii port has the following characteristics: ? capable of supporting both 10 mbps and 100 mbps data rates in half or full duplex modes ? data and delimiters are synchronous to clock references ? provides independent 4-bit wide transmit and receive paths ? uses ttl signal levels ? provides a simple management interface (common to all ports) ? capable of driving a limited length of shielded cable ? supports full auto-negotiation ? supports flow control for full duplex and back pressure for half duplex in addition, for switch expansion, port #13 can work at a clock frequency of up to 60mhz. in this mode the forcelinkpass (daddr[5 and 6] at reset) pin must be pulled down. the gt-482xx incorporates all of the required digital circuitry to interface to 100basetx, 100baset4, and 100basefx. two fast ethernet ports are integrated in the gt-482xx and only a small amount of external logic is needed to implement standard physical interfaces. 8.1 10/100 mii compatible interface the gt-482xx mac allows it to be connected to a 10mbps or 100mbps network. the gt-482xx interfaces to an ieee 802.3 10/100 mbps mii compatible phy device. the data path consists of a separate nibble-wide stream for both transmit and receive activities. the gt-482xx can switch automatically between 10 or 100 mbps operation depending on the speed of the network. data transfers are clocked by 25 mhz transmit and receive clocks in 100 mbps operation, or by 2.5 mhz transmit and receive clocks in 10 mbps operation. the clock inputs are driven by the phy, which controls the clock rate based on auto-negotiation. 8.2 media access control (mac) the gt-482xx mac performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. the gt-482xx ensures that any outgoing packet complies with the 802.3 specification in terms of preamble structure. the gt-482xx transmits 56 preamble bits before start of frame delimiter (sfd). the gt-482xx operates in half-duplex or full-duplex modes. in half-duplex mode, the gt- 482xx checks that there is no competitor for the network bus before transmission. in addition to listening for a clear line before transmitting, the gt-482xx handles collisions in a pre-determined way. if two nodes attempt to transmit at the same time, the signals collide and the data on the line is garbled. the gt-482xx listens while it is transmitting, and it can detect a collision. if a collision is detected, the gt-482xx transmits a jam pattern and then delays its re-transmission for a random time period determined by the backoff algorithm. in full-duplex mode, the gt-482xx transmits unconditionally. 8.3 auto-ne g otiation 8.3.1 disabled auto-negotiation when ddata[27:26] are low at reset, auto-negotiation is disabled for both ports and each port can be selected as half- or full-duplex mode independently. after reset the port mode is set by the state sampled on the ddata[25:24] pin. this value can be overridden in each ports port control register. the operation speed for each port (10mbps or 100mbps) is determined by the frequency of txclk[x] and rxclk[x] generated by the phy. when the port is operating at 10mbps, the phy generates a 2.5mhz clock for both txclk and rxclk. when the port is operating at 100mbps, the phy generates a 25mhz clock for both txclk and rxclk.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 38 revision 1.2 8.3.2 enabled auto-negotiation when ddata[27:26] are high at reset, auto-negotiation is enabled for each port. the gt-482xx decodes the duplex mode for each port from the values of the auto-negotiation advertisement register and the auto-negotia- tion link partner ability registers at the end of the auto-negotiation process. once the duplex mode is resolved, the gt-482xx updates the port control registers with that duplex mode. the gt-482xx continuously performs the following operations for each port (phy addresses 1 and 2 alternately), implemented as read commands issued via the mdc/mdio interface: 1. reads the phy auto-negotiation complete status. when phy bit 1.5 (register 1, bit 5) is '0' switches to half-duplex mode and continues to read phy register bit 1.5. when phy bit 1.5 is '1', signaling auto- negotiation is complete and step two is performed. notes: ? steps 2 through 6 are performed once every time the phy bit 1.5 transitions from '0' to '1'. once phy bit 1.5 remains '1' and phy registers 4 and 5 are read, the gt-482xx continues to read phy register 1, and monitors phy bit 1.5. steps 2 to 6 are performed once, if after rst* de-assertion, the phy bit 1.5 is read as '1', to update the gt-482xx duplex mode. ? phy bit 1.2 (link status) is read and latched during this register read operation, regardless of the auto- negotiation status. 2. reads the auto-negotiation advertisement register, phy register 4 and continues to step 3. 3. reads the auto-negotiation link partner ability register, phy register 5 and continues to step 4. 4. resolves the highest common ability of the two link partners as follows (according to the 802.3u priority resolution clause 28b.3): if (bit 4.8 and bit 5.8) == '1' then ability is 100base-tx full duplex else if (bit 4.9 and bit 5.9) == '1' then ability is 100base-t4 half duplex else if (bit 4.7 and bit 5.7) == '1' then ability is 100base-tx half duplex else if (bit 4.6 and bit 5.6) == '1' then ability is 10base-t full duplex else ability is 10base-t half duplex; continues to step 5. 5. resolves the duplex mode of the two link partners as follows: if ((ability == "100base-tx full duplex") or (ability == "10base-t full duplex")) then duplex mode = full duplex else duplex mode = half duplex; note: the value of the duplex mode indication changes only after reading both phy registers 4 and 5. continues to step 6. 6. updates the port control register by writing the correct duplex mode bit. 8.4 backoff al g orithm options the gt-482xx implements the truncated exponential backoff algorithm defined by the 802.3 standard. aggres- siveness of the backoff algorithm used by all of the ports is controlled by the limit4 pin or bit in the global control register. limit4 controls the number of consecutive packet collisions that occur before the collision counter is reset. when limit4 is low, the gt-482xx resets the collision counter after 16 consecutive retransmit trials, restarts the backoff algorithm, and continues to try to retransmit the frame. the retransmission is performed from the data stored in the dram. in the case of a successful transmission, the gt-482xx is ready to transmit any other frames queued in its transmit fifo within the minimum ipg of the link.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 39 when limit4 is high, the gt-482xx resets its collision counter and restarts the backoff algorithm after 4 consecu- tive transmit trials. as a result the gt-482xx is more aggressive in acquiring the media following a collision. this results in better overall switch throughput (less packet loss) in standardized tests. limit4 can be toggled during switch operation. 8.5 data blinder the data blinder field (datablind in the serial parameters register) sets the period of time during which the port does not look at the wire to decide to transmit (inhibit time.) the default value is 32 bit times. 8.6 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the default (from the standard) is 9.6us for 10mbps ethernet and 960nsec for 100-mbps fast ethernet. the ipg can be programmed to be smaller or larger than the ethernet standards. making the ipg smaller can improve test scores at the cost of ethernet compatibility (a technique used by many vendors during head-to-head magazine tests.) this mode of operation is nor recommended due to violation of ieee standards. ipg is programmable in the serial parameters register. 8.7 10/100 mbps mii transmission when the gt-482xx has a frame ready for transmission, it samples the link activity. if the crs signal is inactive (no activity on the link), and the inter-packet gap (ipg) counter has expired, frame transmission begins. the data is transmitted via pins txd[3:0] of the transmitting port, clocked on the rising edge of txclk. the signal txen is asserted at the same time. in the case of collision, the phy asserts the col signal on the gt-482xx which then stops transmitting the frame and append a jam sequence onto the link. after the end of a collided transmission, the gt-482xx backs off and attempts to retransmit once the backoff counter expires. per ieee 802.3 specification, the clock to output delay must be a minimum of 0ns and a maximum of 25ns as shown in figure 4. figure 4: mii transmit signal timing 8.8 10/100 mbps mii reception frame reception starts with the assertion of crs (while the gt-482xx is not transmitting) by the phy. once rxdv is asserted, the gt-482xx begins sampling incoming data on pins rxdv[3:0] on the rising edge of rxclk. recep- tion ends when the rxdv is deasserted by the phy. the last nibble sampled by the gt-482xx is the nibble present on rxd[3:0] on the last rxclk rising edge in which rxdv is still asserted. during reception, rxdv is asserted. if, while rxdv is asserted, the gt-482xx detects the assertion of rxer, it designates this packet as cor- rupted. while no reception is taking place, rxdv should remain deasserted. the input setup time should be a min- imum of 10ns and the input hold time must be a minimum of 10ns and shown in figure 5. 0ns min 25ns max txclk txd, txen vih min vil max vih min vil max
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 40 revision 1.2 figure 5: mmii receive signal timing 8.9 10/100 mbps full-duplex operation when operating in full-duplex mode the gt-482xx can transmit and receive frames simultaneously. in full-duplex mode, the crs signal is associated with received frames only and has no effect on transmitted frames. the col signal is ignored by the gt-482xx while in full-duplex mode. transmission starts when txen goes active. trans- mission starts regardless of the state of crs. reception starts when the crs and rxdv signals are asserted indi- cating traffic on the receive port of the phy. 8.10 ille g al frames the gt-482xx discards all illegal frames and increments the appropriate error mib counters. for example, runts (less than 64 bytes), oversize (greater than 1518/1536 bytes), and bad fcs (bad checksum). 8.11 partition mode a port enters partition mode when more than 32 consecutive collisions are seen on a 10mbps port, or more than 60 consecutive collisions are seen on a 100mbps port. in partition mode the port continues to transmit but it will not receive. the corresponding bit in the status register is set when a port is partitioned. a port is returned to nor- mal operation mode when a good packet is seen on the wire. 8.11.1 enabling partition mode partition is enabled (for all ports) by setting the enable bit in the gt-482xx control register. the default value is partition disabled for all ports. you must have a cpu in the system to enable partition mode; there is no pin strap- ping option. 8.11.2 entering partition state when partition is enabled, a port enters partition state for any of the following cases: ? the port detects a collision on every one of 32 consecutive retransmit attempts of the same packet on a 10mbps port ? the port detects a collision on every one of 60 consecutive retransmit attempts of the same packet on a 100mbps port ? the port detects a single collision which occurs for more than 512 bit times. while in partition state: ? if the interrupt is not masked, the gt-482xx issues an interrupt to the cpu upon entering partition state, and sets the partition bit of that port in the status register. 10ns min rxclk rxd, rxdv, rxer 10ns min vih min vil max vih min vil max
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 41 ? the port continues to transmit its pending packet, regardless of the collision detection, and does not fol- low the usual backoff algorithm. additional packets pending for transmission, are transmitted, while ignoring the internal collision indication. this frees the port's transmit buffers which would otherwise be filled up at the expense of the other ports' buffers. the assumption is that partition state represents a system failure situation (bad connector/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to full buffers. ? the partition indication is available via the led interface (both the status led - blinking twice, and a ded- icated led - on constantly). 8.11.3 exiting from partition state the port exits from partition state at the end of a successful packet transmission or packet reception. a successful packet transmission is declared if no collisions were detected during packet transmit or receive. if the interrupt is not masked, the gt-482xx issues an interrupt to the cpu upon exiting from partition state, and clears the partition bit of that port in the status register. 8.12 back pressure the gt-482xx implements a back-pressure algorithm when it is operating only in half-duplex mode. back pres- sure is enabled by setting the backpressureen bit in the port control register (also sampled at reset from pin). the gt-482xx enters into back-pressure mode when the buffers allocated to a port exceed the rxthreshold value (the user should not disable the per-port rx buffer threshold when using backpressure). in back-pressure mode, the gt-482xx transmits a jam pattern for a programmable value of time (jam_length). the ipg between two consecutive jam patterns (or between the last transmit and the first jam) is also a programmable value (jam_ipg). when a packet is transmitted during back pressure it is transmitted with a gap of ipg_jam_to_data after the transmission of the jam pattern. 8.13 flow control the gt-482xx implements the ieee 802.3x flow control standard on any full-duplex port. this mode is activated by setting the flowconten bit in the port control register (sampled at reset from pins). when the gt-482xx receives a pause packet it avoids transmitting a new packet from this port for the period of time specified in the received pause packet. a received packet is recognized as flow control if it was received without errors and is either one of the following: ? da = 01-80-c2-00-00-01 and type=88-08 and mac_control_opcode=01 ? da = (the port address) and type=88-08 and mac_control_opcode=01. the 48bit port address is in the registers source_address_low, source_address_high and port_control[sa<3:0>]. this address is used as source address for pause packets that the gt-482xx generates (to da=01-80-c2-00-00-01) the gt-482xx sends a pause packet on a port, when the number of buffers allocated to this port exceed a pro- grammable threshold (as specified by flowcontthrhigh field in rx threshold register. the user should not dis- able the per-port rx buffer threshold when using flow-control. the pause packet will be sent with the parameter equal to 0xffff. the transmitting device is expected to stop transmitting to the specific gt-482xx port for suffi- cient time to enable the gt-482xx to release its buffers. when the number of buffers drops below the flowcont- thrlow number, the gt-482xx sends a pause packet with its parameter equal to 0x0 to indicate to the transmitter that the gt-482xx is ready to receive packets on that link. to prevent deadlocks on the network (due to loss of pause packets), the gt-482xx will periodically send pause packets every 50msec (for the 10mbps ports, every 500msec). pause packets with parameters equal to 0xffff are sent every 50msec when the number of buffers allocated to this port exceed a programmable threshold (flow- contthrhigh). pause packets with parameters equal to 0x0 are send every 50msec when the number of buffers allocated to this port is less than or equal to flowcontthrlow number.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 42 revision 1.2 each port holds its own source address for flow control packets. the source address consists of 44 common bits for all ports and four dedicated bits per port. the common bits (47:4) are held in the source address high and low registers. the four least significant bits are held in the port control registers. 8.14 802.1q vlan ta gg in g support the gt-482xx has the ability to receive and transmit ethernet frames up to 1536 bytes in length, thereby accom- modating the ieee 802.1q standard vlan tagging bytes. this feature is enabled/disabled by bit 13 in the port control register (also sampled from daddr[8] at reset.) the default is to disable this feature. bytes longer than 1536 are discarded as over-size frames. 8.15 mii mana g ement interface (smi) the gt-482xx mac includes an mii management interface (smi) for mii compliant phy devices. this enables the passing of control and status parameters between the gt-482xx and the phy (parameters specified by the cpu) by one serial pin (mdio) and a clocking pin (mdc), and reduces the number of control pins required for phy mode control. typically, the gt-482xx continuously queries the phy devices for their link status, without cpu intervention. the predefined phy addresses for the link query are 1 and 2 (out of possible 32 addresses). this protocol complies with the national dp83840 phy device as well as other available phys. a cpu connected to the gt-482xx has access to all of the phy addresses/registers, by writing and reading to/ from a dedicated set of the gt-482xx smi control registers. the smi allows the cpu to have direct control over an mii-compatible phy device via the gt-482xx smi control register. this allows the driver software to place the phy in specific modes such as full duplex, loopback, power down, 10/100 speed selection as well as control of the phy devices auto-negotiation function, if it exists. the cpu writes commands to the gt-482xx smi register and the gt-482xx reads or writes control/status parameters to the phy device via a serial, bi-directional data pin called mdio. these serial data transfers are clocked by the gt-482xx mdc clock output. the delay time between two consecutive smi write transactions is at least (4x64=256) mdc clock cycles. 8.15.1 smi cycles the smi protocol consists of a bit stream driven or sampled by the gt-482xx on each rising edge of the mdc clock. the bit stream format of the smi frame is described in table 10. ? pre (preamble). at the beginning of each transaction, the gt-482xx sends a sequence of 32 contiguous logic one bits on mdio with 32 corresponding cycles on mdc to provide the phy with a pattern that it can use to establish synchronization. ? st (start of frame). a start of frame pattern of 01. ? op (operation code). 10 - read; 01 - write ? phyad (phy address). a 5 bit address of the phy device (32 possible addresses). the first phy address bit transmitted by the gt-482xx is the msb of the address. ? regad (register address). a 5 bit address of the phy register (32 possible registers in each phy). the first register address bit transmitted by the gt-482xx is the msb of the address. the gt-482xx always queries the phy device for status of the link by reading register 1, bit 2. ? ta (turn around). the turnaround time is a 2 bit time spacing between the register address field and the data field of the smi frame to avoid contention during a read transaction. during a read transaction the phy should not drive mdio in the first bit time and drive 0 in the second bit time. during a write transaction, the gt-482xx drives a 10 pattern to fill the ta time. table 10: smi bit stream format pre st op phyad regad ta data idle read 1...1 01 10 aaaaa rrrrr z0 d..d(16) z write 1...1 01 01 aaaaa rrrrr 10 d..d(16) z
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 43 ? data (data). the data field is 16 bits long. the phy drives the data field during read transactions. the gt-482xx drives the data field during write transactions. the first data bit transmitted and received will be bit 15 of the phy register being addressed. ? idle (idle). the idle condition on mdio is a high impedance state. the mdio driver is disabled and the phy should pull-up the mdio line to a logic one. 8.15.2 smi timing requirements when the mdio signal is driven by the phy, it is sampled by the gt-482xx synchronously with respect to the ris- ing edge of mdc. per ieee 802.3 specification, the mdc to output delay must be a minimum of 0ns and a maxi- mum of 300ns as shown in figure 6. in addition, when the mdio signal is driven by the gt-482xx, the gt-482xx provides a minimum of 10ns of setup time and minimum of 10ns of hold time as shown in figure 7 . figure 6: mdio output delay figure 7: required mdio setup and hold time 8.16 link detection and link detection b y pass (forcelinkpass) typically, the gt-482xx will continuously query the phy devices for its link status, without cpu intervention. the predefined phy addresses for the link query are 1 and 2 (out of possible 32 addresses). the gt-482xx alternately 0ns min 300ns max mdc mdio vih min vil max vih min vil max 10ns min mdc mdio 10ns min vih min vil max vih min vil max
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 44 revision 1.2 reads register 1 from phy1 and phy2 and updates the internal link bits according to the value of bit 2 of register 1. in the case of link is down (bit 2 is 0), that port will enter link test fail state. in this state, all of the ports lo gic is reset. the port will exit from link test fail state only when the link is up (bit 2 of register 1) is read from the ports phy as 1. the gt-482xx provides an option to disable the link detection mechanism by forcing the link state of both ports to the link test pass state. this mode is used also to operate the expansion port. this is done with the daddr[6:5] pins which are sampled at reset. when daddr[6:5] are low on reset, the link status of both ports remains in the link is up state regardless of the phys link bit value. when daddr[6:5] are high on reset, the link status of the ports is read through the smi from the phy devices (register 1, bit 2). 8.17 usin g the mii interfaces to connect two (or more) galax y devices either mii interface can be used to cascade two gt-482xx devices to create a higher port density switch. in such an application, the mii interface can be clocked up to 60mhz providing a non-blocking interconnect for configura- tions of up to 24 ethernet and two fast ethernet ports. more than two galaxy devices may be cascaded, however, such configurations will exhibit blocking in highly-loaded environments/test setups. figure 8: expansion mii wiring diagram txclk rxclk rxd rxdv txd txen col crs rxer txclk rxclk rxd rxdv txd txen col crs rxer vss vss or vdd up to 60mhz
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 45 9. e thernet (10m bps ) i nterfaces the gt-482xx incorporates all the required digital circuitry to interface to 10base-t and 10base-fl. one of the 12 ports can work in aui mode. 9.1 media access control (mac) the gt-482xx operates in half-duplex or full-duplex modes. in half-duplex mode, the gt-482xx checks that there is no competitor for the network bus before transmission. in addition to listening for a clear line before transmitting, the gt-482xx handles collisions in a pre-determined way. if two nodes attempt to transmit at the same time, the signals collide and the data on the line is garbled. the gt-482xx listens while it is transmitting, and can detect a collision. if a collision is detected, the gt-482xx transmits a jam pattern and then delays its re-transmission for a random time period determined by the backoff algorithm. in full-duplex mode, the gt-482xx transmits uncondi- tionally. 9.2 ille g al frames the gt-482xx discards all illegal frames and increments the appropriate error mib counters. for example, runts (less than 64 bytes), oversize (greater than 1536 bytes), and bad fcs (bad checksum.) 9.3 duplex mode selection each port can be independently selected to function in half- or full-duplex mode. following reset the port mode is set by the state sampled on the txde[x] pin. this value can be overridden in each ports port control register. 9.4 backoff al g orithm options the backoff algorithm used by all ports is controlled by the limit4 pin or bit in the global control register. limit4 controls the number of consecutive packet collisions that occur before the collision counter is reset. as a result of asserting the pin or bit results, the gt-482xx is more aggressive in acquiring the media following a collision. this results in improved overall switch throughput (less packet loss) in standardized tests. limit4 can be toggled during switch operation. 9.5 manchester encoder/decoder the manchester encoder receives clocked data from the transmit engine and uses an internal 20mhz clock (80mhz divided by 4) to provide the manchester-encoded data to the physical interface. the manchester decoder uses the 80mhz clock to recover the receive clock and to sample the incoming data. 9.6 link inte g rit y the gt-482xx implements the link integrity test as specified in the ieee 802.3 10base-t and 10base-fl supple- ments. 9.7 data blinder the data blinder field (datablind in the serial parameters register) sets the period of time. the port does not look at the wire to decide to transmit (inhibit time.) the default value of the data blinder is 32us. the programmed value in the register is the difference between 96us and the required data blinder length. 9.8 inter-packet gap (ipg) ipg is the idle time between any two successive packets transmitted from the same port. the default (from the standard) is 9.6us for 10mbps ethernet and 960nsec for 100-mbps fast ethernet. the ipg can be programmed to be smaller or larger than the ethernet standards. making the ipg smaller can improve test scores at the cost of ethernet compatibility (a technique used by many vendors during head-to-head magazine tests). however, this mode of operation is not recommended due to violation of ieee standards.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 46 revision 1.2 ipg is programmable in the serial parameters register. 9.9 partition mode a port enters partition mode when more than 32 consecutive collisions are seen on the port. when in partition mode, the port continues to transmit but does not receive. the corresponding bit in the status register is set when a port is partitioned. a port is returned to normal operation mode when a good packet is seen on the wire. 9.9.1 enabling partition mode partition is enabled (for all ports) by setting the enable bit in the gt-482xx control register. the default value is partition disabled for all ports. you must have a cpu in the system to enable partition mode; there is no pin strap- ping option. 9.9.2 entering partition state when partition is enabled, a port will enter partition state when either of the following two situations occur: ? the port detects a collision on every one of 32 consecutive retransmit attempts of the same packet. ? the port detects a single collision which occurs for more than 2048 bit times (i.e. most likely to occur in aui mode). while in partition state: ? if the interrupt is not masked, the gt-482xx will issue an interrupt to the cpu upon entering partition state, and will set the partition bit of that port in the status register. ? the port will continue to transmit its pending packet, regardless of the collision detection, and will not fol- low the usual backoff algorithm. a more aggressive backoff algorithm is in progress which is similar to the backoff algorithm when limit4 is activated. additional packets pending for transmission are transmit- ted, while ignoring the internal collision indication. this frees the port's transmit buffers which would oth- erwise be filled up at the expense of the other ports' buffers. the assumption is that partition is a system failure situation (bad connector/cable/station), thus losing the transmitted packets is a small price to pay versus the cost of halting the switch by filling up all of its buffers. ? the partition indication is available via the led interface (both the status led - blinking twice, and a dedi- cated led - on constantly). 9.9.3 exiting from partition state the port will exit from partition state at the end of a successful packet transmission. a successful packet transmis- sion will be declared, provided no collisions were detected on the first 512 bits of the transmission. if the interrupt is not masked, the gt-482xx issues an interrupt to the cpu upon exiting from partition state, and clears the parti- tion bit of that port in the status register. 9.10 802.1q vlan ta gg in g support the gt-482xx has the ability to receive and transmit ethernet frames up to 1536 bytes in length, thereby accom- modating the ieee 802.1q standard vlan tagging bytes (four extra bytes or more.) this feature is enabled/dis- abled by bit 13 in the port control register. the default is to disable this feature. bytes longer than 1536 are discarded as over-size frames. 9.11 back pressure back-pressure support in the 10mbps ports is identical to the support for the 100mbps ports, described previously. 9.12 flow control flow control support in the 10mbps ports is identical to the support for the 100mbps ports, described previously.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 47 9.13 serial modes each ethernet port can operate in one of three serial modes: 10baset, 10basefl, or aui, the serial mode is set after reset by the state of ddata[23:0]. these values can be overwritten in the port control register. 9.14 ph y sical interface circuitr y since the digital portion of the ethernet phy is integrated in the gt-482xx, only a small amount of external logic is needed to implement the standard physical interfaces. the gt-482xx interfaces directly with the amds quiet? chip (by setting the gt-482xx to work in pseudo-aui mode) or with the tamarack tc3001 (setting the gt-482xx to work in 10base-t mode). information about the tamarack tc3001 can be found at the following url: www.tmi.com.tw. information about the amd quiet chip can be found at the following url: www.amd.com. schematics for both implementations are available upon request. note: galileo technology may support other physical interfaces in the future. please contact your local galileo technology fae for further updates. 9.15 serial link status indication this link is used to serially shift the link status of ports 1 to 11 from the external phy. ledclk and ledstb are used to clock and strobe the data (assertion of ledstb indicates the beginning of the link data stream). the serial link status indication of port 0 is provided separately at linkstatus[0] pin. figure 9 illustrates a port 1 link fail. figure 9: example of serial link status indicator of port 1 link fail ledclk ledstb serlinkstatus indication port # 1 2 3 ...... .......... ... .... port1 link fail
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 48 revision 1.2 10. e nabling /d isabling p orts the gt-482xx ports can be enabled and disabled depending by a combination of: ? an external hardware pin, endev* (low - device enabled, high - device disabled) ? enabledevice, bit 20 of the global control register (0 - device status based on endev*, 1 - device enabled) ? porten, bit 0 of each port control register, (0 - port disabled, 1 - port enabled) when a port is disabled, no packets are received or transmitted from the serial ports or the cpu bus. even though ports are disabled, the cpu can read from and write to the gt-482xxs registers. see table 11 for the enabling or disabling of the gt-482xx ports. table 11: enabling/disabling ports of the gt-482xx endev* pin enabledevice bit porten bit port status low 0 0 disabled low 0 1 enabled low 1 0 disabled low 1 1 enabled high 0 0 disabled high 0 1 disabled high 1 0 disabled high 1 1 enabled
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 49 11. n etwork m anagement s upport the gt-482xx supports the following management features: ? repeater mib counters ? port monitoring (sniffer) mode ? spanning tree bpdu detection ? broadcast storm filtering ? hp-ease packet sampling technology the packet sampling (hp-ease) functions are described in section 12. 11.1 repeater mib counters the gt-482xx incorporates a full set of repeater mib counters for each ethernet port. counters are accessed by the management cpu through the cpu interface. the repeater mib counters include the following data: ? bytes received ? bytes sent ? frames received ? frames sent ? total bytes received (good and bad) ? total frames received (good and bad) ? multicast frames received ? broadcast frames received ? crc + alignment error ? oversize frames ? fragments ? jabber frames ? collision ? late collision ? frames with length of 64 bytes ? frames with length of between 65-127 bytes ? frames with length of between 128-255 bytes ? frames with length of between 256-511 bytes ? frames with length of between 512-1023 bytes ? frames with length of between 1024-1518/1536 bytes ? mac receive error (received packets with rxer asserted) - only for 100mbps ports ? dropped frames see the table 63, port mib counters, on page 109 for detailed information on the repeater mib counter regis- ters. 11.2 monitorin g (sniffer) mode the cpu can program the gt-482xx to work in monitoring mode for one of the ethernet ports. in monitoring mode, the gt-482xx sends all received (including local traffic) to the cpu, or to another port in the same gt- 482xx device which is assigned to be the sniffer. the packets that are forwarded to the sniffer are not necessarily in a linear time order. monitored packets are also forwarded as normal to their output port. sniffer packets (packets that are being sent to target sniffer) are queued to the same priority queue as the original packet. monitoring mode is enabled by setting the sniffer register fields. only one port of a single gt-482xx device can work in monitoring mode at a time.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 50 revision 1.2 when monitoring is implemented in a multi-device configuration and connected together through the expansion port, the user cannot set the source sniffer and the target sniffer in the different devices. this requires using the expansion port as target sniffer in the source device, and as source sniffer in the target device and will cause unre- lated traffic between the devices to be forwarded to the target-sniffer port on the other device. for such configuration the recommended operation should be one of the following: a) designate the cpu as the target sniffer, or b) restrict the source and the target sniffer port to reside in the same device 11.3 spannin g tree (bpdu) support the gt-482xx provides hardware assistance for the bridge spanning tree algorithm. the spanning tree algo- rithm itself is performed by a management cpu. the gt-482xx includes a spanen bit in the global control register and additional spanen bits in each of the 14 port control registers. table 12 summarizes the hardware assistance for the spanning tree algorithm. note : the gt-482xx does not learn mac addresses during the spanning tree learning stage (it is learning the bridge topology while in this mode.) the gt-482xx only learns mac addresses in the forward mode. 11.4 broadcast storm filterin g excessive broadcast packets (broadcast storms) can be filtered in a managed switch by setting the filbroad bit in the port control register. in this mode, the inbound broadcast packets will be discarded. broadcast packets can be re-enabled once the loops causing the broadcast storm are eliminated via the spanning tree algorithm. table 12: spanning tree enable bit definition spanen (global) spanen (port) logic state remarks 0 x port enable no spanning tree. treat bpdu as regular multicast 1 1 blocking, listening, learning transfer bpdus to cpu. all receive/transmit packets should be rejected. accept bpdu messages from the cpu. no address learning 1 0 forward transfer bpdu to the cpu. accept all packets. address learning
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 51 12. p acket s ampling t echnology (hp-ease) the gt-482xx supports a packet sampling technology developed by hewlett-packard called the embedded advanced sampling environment (hp ease). this packet sampling technology can be use to implement many of the management functions that rmon provides, but at a greatly reduced implementation cost. with the gt-482xx device, the switch oem has the freedom to implement true rmon, sampled rmon, ease, or any of the above. note: customers wishing to use the packet sampling technology to implement a true hp-ease agent should contact galileo directly for additional information and mib specifications. 12.1 packet samplin g overview hp ease sampling requires a counter for each network segment. this counter indicates the number of packets to be skipped before a sample is taken. when the counter reaches zero, the next packet on the network segment is captured by the network device. software then truncates the sampled packet, to some small fixed length, and appends a snapshot of specific mib counters for that segment. the counter snapshot does not have to be taken simultaneously with the sample. software may introduce a delay of some milliseconds after the packet is sampled by hardware, however minimizing this delay makes ease more accurate. the newly created datagram is sent off to the network management station as an snmp trap. the network management station records the sample and counters in a database, and uses the information to obtain traffic load estimates, top talker matrices, high-level protocol flows, and other useful sets of information. after the sample has been taken, the cpu loads the count- down counter with the next skip count to capture the next sampled packet. the skip count is a random value loaded by software. ease software in the network device must keep track of the last receive error sources and the associated error conditions. the network device keeps track of errors associated with received packets and informs the cpu of the source address (sa) of these error packets. 12.2 ease functionalit y on the gt-482xx support for ease sampling is directly integrated in the gt-482xx chip, but requires the presence of a cpu in order to function, for enabling the ease support as well as the sample packet processing. each gt-482xx device supports 14 network segments (one per port) as well as the cpu system bus. sampling will occur only on the net- work segments, and sampled packets will be sent to the cpu. sampling is not performed on the cpu bus. it may, however, be performed on packets received from the cpu, but only as a function of the counters for the destina- tion ports (i.e. packets entering the gt-482xx via the cpu bus and being transmitted through one or more ports). there is no counter for the cpu interface itself. only good packets of valid length are sampled. all other packets are not sampled and do not affect the skip count. all counters and registers implemented in the gt-482xx chip in order to support ease functionality, may be accessed by the cpu. 12.3 ease re g ister a register is defined for each external port supported on the gt-482xx device. this register is used by the cpu to load the internal count down counter, described above, with a random skip count. the count-down counter is 20 bits in length and is used to actually determine when a sample is to be made. the gt-482xx implements a shadow register for each of the ease registers. the shadow register address is the same address as the ease_register address. after a value has been written to the ease register it is transferred to an internal 1 word deep fifo (the shadow register) or directly to the actual count-down counter if that counter is currently idle and empty. if the value can not be transferred to the count-down counter, the value will be held in the ease_register shadow register until space becomes available (i.e. a sample has been taken). if the ease_register shadow reg- ister was written and the cpu does attempt to write a new value, the new value will silently replace the existing value. if the ease_register is empty at the time a new value needs to be loaded into the internal counter or the shadow register, the gt-482xx will load the previous value. ease is effectively disabled on that port.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 52 revision 1.2 12.4 ease interrupts a status bit indicating the full/empty status of the ease_register for each external port supported on the gt- 482xx, is maintained as part of the interrupt cause register. when a value is moved from the ease_register into an internal counter or shadow register, a bit is reset in the interrupt cause register indicating that the ease_register is now empty. setting this bit should also generate a processor interrupt. the interrupt cause reg- ister may be read to determine the state of the ease_registers, and may be written to clear the interrupt condition described above. it is possible for the cpu to mask the interrupt condition as well as clear the interrupt condition. the gt-482xx implements a mask bit in the interrupt mask register for each ease status bit in the interrupt cause register. masking and clearing the interrupts are executed in a way that is consistent with the other interrupts sup- ported by the gt-482xx. 12.5 sampled packet indication sampled packets are sent to the cpu. the sample indication bits in the descriptor specify which ports on the par- ticular gt-482xx this sample is associated with. it is possible for a single sample to be associated with more than one port at a time. for example, a broadcast packet flooded to all ports may be sampled on several ports if each of their skip counters had previously been decremented to zero. each gt-482xx device operates independently, therefore the cpu can receive the same sample from different gt-482xx devices. for example, a broadcast packet flooded to all ports in the system may be sampled by several gt-482xxs at the same time. each sample results in a separate copy of the packet being sent to the cpu. pack- ets which would normally be received by the cpu can also be sampled. in this case, only a single copy of the packet can be sent to the cpu. the cpu is responsible for determining if a sampled packet should be accepted as a normal receive packet. in the case where a normally received packet is also a sample from multiple the gt- 482xx devices (e.g. a broadcast packet). the gt-482xx must provide an indication to avoid the cpu from pro- cessing duplicate packets. 12.6 error source indications ease software in the network device must keep track of the last receive error sources and the associated error conditions. the gt-482xx informs the cpu of error source conditions by sending a new_address message. two types of errors are defined for this procedure: fcs error and frames too long. when the gt-482xx receives a packet with any of the above conditions, it will send an error_source message to the cpu. the error_source message will contain the 48-bit source address of the error packet, the source port number and an indication of the error type. 12.7 enablin g /disablin g ease functionalit y an explicit hp ease enable/disable bit is provided in the global control register for the gt-482xx device. when hp ease is disabled using this bit, no ease samples nor error_source messages are sent to the cpu. hp ease packet sampling can be disabled on a port anytime the internal counter can not be reloaded with a new skip count because the cpu has not provided any new values via the ease_register. interrupt conditions generated by an empty ease_register can be masked by appropriate bits in the ease_full_mask and/or interrupt cause registers. the following algorithm enables ease for the first time: 1. enable ease in the global control register. 2. enable ease in the port control register per port (10mbit ports - bit [8], 100mbit ports - bits [3:2] of pcr12). 3. write a skip value to the ease register of each port.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 53 the following algorithm disables ease: 1. disable ease per port in the pcr. 2. disable ease in the global control register. note : if some of the ports have their ease enable bit enabled, the gcr bit must be enabled. if the cpu failed loading a new value to the ease register skip counter, the old value will be used and the ease mechanism will continue sampling.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 54 revision 1.2 13. led s upport the serial led interface in the gt-482xx is similar to the 3-pin led interface of the gt-48001a device which requires a pal to interpret the led bit stream. galileo technology provides reference designs and example pal equations in the led interface application note available from our website. 13.1 led indications interface description table 13 on page 54 details the accessible data on the led indications serial interface for each of the gt-482xx ports. 13.2 detailed led si g nal description the led signals and their activation conditions are described in the following sections. 13.2.1 primary port status led the primary port status led indicates the port status in two operation modes, selectable via the ledmode input (ledstb pin sampled at reset). 13.2.1.1 primary port status led in mode 0: (ledmode input is low) in this mode, the port status led provides the following information: if port is disabled port status led is off; else if link inte g rit y test failed port status led blinks once; else if partition state detected port status led blinks twice; else ever y thin g is ok ( port status led is on ) 13.2.1.2 status led blink timing (mode 0) link integrity test failed, status led blinks once. primary status bit is active for 500 ms every 5 secs. partition, status led blinks twice. primary status bit is activated twice every 5 secs for 500 ms each time, with a period of 1500 ms between two consecutive activations. table 13: led signals available data description symbolic signal name type primary port status led primary_port_status n/a transmit data in progress transmit dynamic receive data in progress receive dynamic transmit/receive data in progress activity dynamic collision active collision dynamic forwarding of unknown packets enabled unknown_enable static the port is configured as sniffer port_is_sniffer static full/half duplex full_duplex static receive buffer full rx_buffer_full dynamic
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 55 figure 10: primary status led timing (one blink). figure 11: primary status led timing (two blinks) 13.2.2 transmit data in progress this signal indicates the port is transmitting data. 13.2.3 receive data in progress this signal indicates port receive activity. 13.2.4 collision active this signal indicates the port collision event detected by the port. 13.2.5 full/half duplex this signal indicates the port duplex: active - full duplex, inactive - half duplex. 13.2.6 receive buffer full this signal indicates the port receive buffer status: active - the buffer exceeds it's programmed threshold, inactive otherwise. 500ms 5sec link inter g it y test fails: primar y status led blinks 500ms ever y 5sec 500ms 5sec port partitioned: primar y status led twice for 500 ms ever y 5 sec 500ms 1500 ms
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 56 revision 1.2 13.2.7 forwarding of unknown packets enabled this signal indicates the port mode of forwarding unknown packets: active - forwarding unknown packets enabled, inactive otherwise. 13.2.8 port configured as sniffer this signal indicates if the port mode is configured as a sniffer target port: active - port is a target sniffer, inactive otherwise. 13.2.9 link fail state this signal indicates the port link status: active - link is down, inactive - link is up. 13.2.10 partition state this signal indicates the port partition status: active - port entered partition state, otherwise inactive. 13.2.11 secondary port status led indicates the secondary status mode as per the inverted value of ledmode input. 13.2.12 pure port status led this signal will be inactive for any of the following events: ? port is disabled ? link integrity test failed ? partition state detected otherwise, this signal is active. 13.3 led si g nal timin g t y pes 13.3.1 static led signals these signals are stable for relatively long time periods. the led indication directly reflects their current value. the static signals are: ? port status (ledmode 0) ? forwarding of unknown packets enabled ? port configured as sniffer ? full/half duplex 13.3.2 dynamic internal signals these signals are typically active for short time periods. in order to be visible through the led indication inter- faces, the gt-482xx includes a "monostable" function per each of these dynamic signals so they can be viewed on the led indication output for a period of about 62 ms in ledmode 0 and 7.5 ms in ledmode 1. the dynamic signals are: ? port status (ledmode 1) ? transmit data in progress (txen) ? receive data in progress (rxdv) ? collision active (col) ? receive buffer full
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 57 13.4 led interface description the led serial interface consists of three outputs: ? ledclk : ledclk is the primary timebase of the led indications interface. it is a 50% duty cycle free run- ning clock at a fixed frequency selectable via the ledmode input. if ledmode is low, ledclk will be 1 mhz. if ledmode is high, ledclk will be 202 khz. ledclk is active when rst* is asserted. ledclk will be floated during rst*. ? ledstb : ledstb (active high) in mode0, indicates the beginning of the data frame. it is activated for a duration of one ledclk cycle once every 256 ledclk cycles, starting from rst* deactivation. this signal marks the beginning of the 256 bit long led data frame. ledstb in mode1 is asserted for the first 56 bit stream. ledstb transitions occur 90 ns after ledclk rising edge. ? leddata : the internal signals are multiplexed on the leddata output for every data frame. leddata transitions occur 90 ns after ledclk rising edge. all internal signals accessible via leddata are active high internally and are inverted on the leddata output (i.e. when an internal signal is active, the data bit on the leddata output will be low). for example: if port 0 transmits data, the internal_event_transmit[0] signal is active high and the corresponding bit 9 in the leddata serial stream is low. the timings for the led serial interface are shown in figure 12. figure 12: serial led interface timings 13.4.1 table of internal activities/status driven via the serial led interface the following tables provide a bit description of the internal signals driven through the led indications serial inter- face. the bit numbers refer to the activation of ledstb. ledstb is active for bit# 1. reserved bit contents are not defined (i.e. can be either high or low). table 14: led signals for mode0 bit number signal bit number signal 1 primary_port_status[0] 106 transmit[7] 2 primary_port_status[1] 107 receive[7] 3 primary_port_status[2] 108 collision[7] 4 primary_port_status[3] 109 rx_buffer_full[7] 5 primary_port_status[4] 110 unknown_enable[7] ledclk 1us 90ns 90ns ledstb leddata or 4.95us
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 58 revision 1.2 6 primary_port_status[5] 111 port_is_sniffer[7] 7 primary_port_status[6] 112 full_duplex[7] 8 primary_port_status[7] 113 transmit[8] 9 primary_port_status[8] 114 receive[8] 10 primary_port_status[9] 115 collision[8] 11 primary_port_status[10] 116 rx_buffer_full[8] 12 primary_port_status[11] 117 unknown_enable[8] 13 primary_port_status[12] 118 port_is_sniffer[8] 14 primary_port_status[13] 119 full_duplex[8] 15 reserved 120 transmit[9] 16 reserved 121 receive[9] 17 reserved 122 collision[9] 18 reserved 123 rx_buffer_full[9] 19 reserved 124 unknown_enable[9] 20 reserved 125 port_is_sniffer[9] 21 reserved 126 full_duplex[9] 22 reserved 127 transmit[10] 23 reserved 128 receive[10] 24 reserved 129 collision[10] 25 reserved 130 rx_buffer_full[10] 26 reserved 131 unknown_enable[10] 27 reserved 132 port_is_sniffer[10] 28 reserved 133 full_duplex[10] 29 reserved 134 transmit[11] 30 reserved 135 receive[11] 31 reserved 136 collision[11] 32 reserved 137 rx_buffer_full[11] 33 reserved 138 unknown_enable[11] 34 reserved 139 port_is_sniffer[11] 35 reserved 140 full_duplex[11] 36 reserved 141 transmit[12] 37 reserved 142 receive[12] 38 reserved 143 collision[12] 39 reserved 144 rx_buffer_full[12] 40 reserved 145 unknown_enable[12] table 14: led signals for mode0 (continued) bit number signal bit number signal
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 59 41 reserved 146 port_is_sniffer[12] 42 reserved 147 full_duplex[12] 43 reserved 148 transmit[13] 44 reserved 149 receive[13] 45 reserved 150 collision[13] 46 reserved 151 rx_buffer_full[13] 47 reserved 152 unknown_enable[13] 48 reserved 153 port_is_sniffer[13] 49 reserved 154 full_duplex[13] 50 reserved 155 link_test_fail[0] 51 reserved 156 link_test_fail[1] 52 reserved 157 link_test_fail[2] 53 reserved 158 link_test_fail[3] 54 reserved 159 link_test_fail[4] 55 reserved 160 link_test_fail[5] 56 reserved 161 link_test_fail[6] 57 transmit[0] 162 link_test_fail[7] 58 receive[0] 163 link_test_fail[8] 59 collision[0] 164 link_test_fail[9] 60 rx_buffer_full[0] 165 link_test_fail[10] 61 unknown_enable[0] 166 link_test_fail[11] 62 port_is_sniffer[0] 167 link_test_fail[12] 63 full_duplex[0] 168 link_test_fail[13] 64 transmit[1] 169 partition[0] 65 receive[1] 170 partition[1] 66 collision[1] 171 partition[2] 67 rx_buffer_full[1] 172 partition[3] 68 unknown_enable[1] 173 partition[4] 69 port_is_sniffer[1] 174 partition[5] 70 full_duplex[1] 175 partition[6] 71 transmit[2] 176 partition[7] 72 receive[2] 177 partition[8] 73 collision[2] 178 partition[9] 74 rx_buffer_full[2] 179 partition[10] 75 unknown_enable[2] 180 partition[11] table 14: led signals for mode0 (continued) bit number signal bit number signal
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 60 revision 1.2 76 port_is_sniffer[2] 181 partition[12] 77 full_duplex[2] 182 partition[13] 78 transmit[3] 183 secondary_port_status[0] 79 receive[3] 184 secondary_port_status[1] 80 collision[3] 185 secondary_port_status[2] 81 rx_buffer_full[3] 186 secondary_port_status[3] 82 unknown_enable[3] 187 secondary_port_status[4] 83 port_is_sniffer[3] 188 secondary_port_status[5] 84 full_duplex[3] 189 secondary_port_status[6] 85 transmit[4] 190 secondary_port_status[7] 86 receive[4] 191 secondary_port_status[8] 87 collision[4] 192 secondary_port_status[9] 88 rx_buffer_full[4] 193 secondary_port_status[10] 89 unknown_enable[4] 194 secondary_port_status[11] 90 port_is_sniffer[4] 195 secondary_port_status[12] 91 full_duplex[4] 196 secondary_port_status[13] 92 transmit[5] 197 pure_port_status[0] 93 receive[5] 198 pure_port_status[1] 94 collision[5] 199 pure_port_status[2] 95 rx_buffer_full[5] 200 pure_port_status[3] 96 unknown_enable[5] 201 pure_port_status[4] 97 port_is_sniffer[5] 202 pure_port_status[5] 98 full_duplex[5] 203 pure_port_status[6] 99 transmit[6] 204 pure_port_status[7] 100 receive[6] 205 pure_port_status[8] 101 collision[6] 206 pure_port_status[9] 102 rx_buffer_full[6] 207 pure_port_status[10] 103 unknown_enable[6] 208 pure_port_status[11] 104 port_is_sniffer[6] 209 pure_port_status[12] 105 full_duplex[5] 210 pure_port_status[13] 211-256 reserved table 14: led signals for mode0 (continued) bit number signal bit number signal
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 61 table 15: led signals for mode1 bit number signal bit number signal 1 link_test_pass/override[0] 106 transmit[7] 2 link_test_pass/override[0] 107 receive[7] 3 link_test_pass/override[1] 108 collision[7] 4 link_test_pass/override[1] 109 rx_buffer_full[7] 5 link_test_pass/override[2] 110 unknown_enable[7] 6 link_test_pass/override[2] 111 port_is_sniffer[7] 7 link_test_pass/override[3] 112 full_duplex[7] 8 link_test_pass/override[3] 113 transmit[8] 9 link_test_pass/override[4] 114 receive[8] 10 link_test_pass/override[4] 115 collision[8] 11 link_test_pass/override[5] 116 rx_buffer_full[8] 12 link_test_pass/override[5] 117 unknown_enable[8] 13 link_test_pass/override[6] 118 port_is_sniffer[8] 14 link_test_pass/override[6] 119 full_duplex[8] 15 link_test_pass/override[7] 120 transmit[9] 16 link_test_pass/override[7] 121 receive[9] 17 link_test_pass/override[8] 122 collision[9] 18 link_test_pass/override[8] 123 rx_buffer_full[9] 19 link_test_pass/override[9] 124 unknown_enable[9] 20 link_test_pass/override[9] 125 port_is_sniffer[9] 21 link_test_pass/override[10] 126 full_duplex[9] 22 link_test_pass/override[10] 127 transmit[10] 23 link_test_pass/override[11] 128 receive[10] 24 link_test_pass/override[11] 129 collision[10] 25 link_test_pass/override12] 130 rx_buffer_full[10] 26 link_test_pass/override[12] 131 unknown_enable[10] 27 link_test_pass/override[13] 132 port_is_sniffer[10] 28 link_test_pass/override[13] 133 full_duplex[10] 29 activity[0] 134 transmit[11] 30 full_duplex[0] 135 receive[11] 31 activity[1] 136 collision[11] 32 full_duplex[1] 137 rx_buffer_full[11] 33 activity[2] 138 unknown_enable[11] 34 full_duplex[2] 139 port_is_sniffer[11] 35 activity[3] 140 full_duplex[11]
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 62 revision 1.2 36 full_duplex[3] 141 transmit[12] 37 activity[4] 142 receive[12] 38 full_duplex[4] 143 collision[12] 39 activity[5] 144 rx_buffer_full[12] 40 full_duplex[5] 145 unknown_enable[12] 41 activity[6] 146 port_is_sniffer[12] 42 full_duplex[6] 147 full_duplex[12] 43 activity[7] 148 transmit[13] 44 full_duplex[7] 149 receive[13] 45 activity[8] 150 collision[13] 46 full_duplex[8] 151 rx_buffer_full[13] 47 activity[9] 152 unknown_enable[13] 48 full_duplex[9] 153 port_is_sniffer[13] 49 activity[10] 154 full_duplex[13] 50 full_duplex[10] 155 link_test_fail[0] 51 activity[11] 156 link_test_fail[1] 52 full_duplex[]11 157 link_test_fail[2] 53 activity[12] 158 link_test_fail[3] 54 full_duplex[]12 159 link_test_fail[4] 55 activity[13] 160 link_test_fail[5] 56 full_duplex[13] 161 link_test_fail[6] 57 transmit[0] 162 link_test_fail[7] 58 receive[0] 163 link_test_fail[8] 59 collision[0] 164 link_test_fail[9] 60 rx_buffer_full[0] 165 link_test_fail[10] 61 unknown_enable[0] 166 link_test_fail[11] 62 port_is_sniffer[0] 167 link_test_fail[12] 63 full_duplex[0] 168 link_test_fail[13] 64 transmit[1] 169 partition[0] 65 receive[1] 170 partition[1] 66 collision[1] 171 partition[2] 67 rx_buffer_full[1] 172 partition[3] 68 unknown_enable[1] 173 partition[4] 69 port_is_sniffer[1] 174 partition[5] 70 full_duplex[1] 175 partition[6] table 15: led signals for mode1 (continued) bit number signal bit number signal
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 63 71 transmit[2] 176 partition[7] 72 receive[2] 177 partition[8] 73 collision[2] 178 partition[9] 74 rx_buffer_full[2] 179 partition[10] 75 unknown_enable[2] 180 partition[11] 76 port_is_sniffer[2] 181 partition[12] 77 full_duplex[2] 182 partition[13] 78 transmit[3] 183 secondary_port_status[0] 79 receive[3] 184 secondary_port_status[1] 80 collision[3] 185 secondary_port_status[2] 81 rx_buffer_full[3] 186 secondary_port_status[3] 82 unknown_enable[3] 187 secondary_port_status[4] 83 port_is_sniffer[3] 188 secondary_port_status[5] 84 full_duplex[3] 189 secondary_port_status[6] 85 transmit[4] 190 secondary_port_status[7] 86 receive[4] 191 secondary_port_status[8] 87 collision[4] 192 secondary_port_status[9] 88 rx_buffer_full[4] 193 secondary_port_status[10] 89 unknown_enable[4] 194 secondary_port_status[11] 90 port_is_sniffer[4] 195 secondary_port_status[12] 91 full_duplex[4] 196 secondary_port_status[13] 92 transmit[5] 197 pure_port_status[0] 93 receive[5] 198 pure_port_status[1] 94 collision[5] 199 pure_port_status[2] 95 rx_buffer_full[5] 200 pure_port_status[3] 96 unknown_enable[5] 201 pure_port_status[4] 97 port_is_sniffer[5] 202 pure_port_status[5] 98 full_duplex[5] 203 pure_port_status[6] 99 transmit[6] 204 pure_port_status[7] 100 receive[6] 205 pure_port_status[8] 101 collision[6] 206 pure_port_status[9] 102 rx_buffer_full[6] 207 pure_port_status[10] 103 unknown_enable[6] 208 pure_port_status[11] 104 port_is_sniffer[6] 209 pure_port_status[12] table 15: led signals for mode1 (continued) bit number signal bit number signal
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 64 revision 1.2 105 full_duplex[5] 210 pure_port_status[13] 211-256 reserved table 15: led signals for mode1 (continued) bit number signal bit number signal
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 65 14. i nterrupts the gt-482xx signals interrupts to a management cpu via the int* pin. interrupts are maskable through the inter- rupt mask register and the interrupt source is determined through the interrupt cause register. interrupts are cleared by writing 0 to the corresponding bit in the interrupt cause register. writing 1 to a bit in the cause regis- ter has no effect.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 66 revision 1.2 15. reset c onfiguration the gt-482xx uses several pins as configuration inputs to set certain parameters following a reset. the defini- tion of the configuration pins changes immediately after reset to their normal function. 15.1 confi g uration pins configuration pins must be externally pulled up or down at reset to select the desired operational parameter. the recommended value of the pull-up/down resistors is 4.7k ohms. table 16 shows the configuration pins for the gt-482xx. it is recommended to pull up the pins for unmanaged systems unless the user chooses to set a specific feature, for example, pull down the ddata[23:0] to set the ports to 10base-t. table 16: reset pin strapping options pin configuration function daddr[4:0] gt-482xx base address daddr[5] forcelinkpass12 0- 1- force link do not force link daddr[6] forcelinkpass13 0- 1- force link do not force link daddr[7] disable transmit watchdog 0- 1- disable enable daddr[8] virtual lan tagging packet extension mode 0- 1- accept packets up to 1518 bytes in length accept packets up to 1536 bytes in length daddr[9] skip init 0- 1- skip initialization do not skip initialization daddr[10] disable buffer threshold 0- 1- disable (dynamic buffer allocation) enable (fixed buffer allocation) daddr[11] backpressure enable/disable 0- 1- disable enable ddata[23:0] 10mbps serial mode (two bits per port, ddata[1:0] for port 0, ddata[3:2] for port 1,...,ddata[23:22] for port 11) 00 01 10 11 10base-t 10base-fl aui reserved ddata[24] full duplex mode for port #12
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 67 0- 1- half duplex full duplex ddata[25] full duplex mode for port #13 0- 1- half duplex full duplex ddata[26] auto-negotiation enable for port #12 0- 1- disable enable ddata[27] auto-negotiation enable for port #13 0- 1- disable enable ddata[28] flow control enable for 10mbps ports 0- 1- disable enable ddata[29] flow control enable for port #12 0- 1- disable enable ddata[30] flow control enable for port #13 0- 1- disable enable ddata[31] head-of-line blocking prevention 0- 1- enable disable burstaddr[1] enable expansion priority on port 13. 0- 1- enable disable txde[11:0] full duplex mode for the 10mbps ports 0- 1- half full dqm dram size 0- 1- 1mbyte 4mbyte ras*, cas*, we* cpu type 000 see text. not used in GT-48207. ledstb led mode 0- 1- led mode 0 led mode 1 table 16: reset pin strapping options (continued) pin configuration function
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 68 revision 1.2 15.2 confi g uration input timin g s the configuration inputs have two timing requirements: ? setup/hold time to clock (as any synchronous input) ? setup of at least 10 clock cycles before reset de-assertion (rising edge). to ensure that these parameters are set, use resistors to strap the configuration pins and delay reset de-asser- tion for at least 10 clock cycles after the clock is stable. txen[0] aui type 0- 1- the inter-packet gap will restart at the end of txen, ignoring any loopback of txd back to rxd. this mode is compatible with the gt-48001. the inter-packet gap will restart when there is no transmit or receive activity. table 16: reset pin strapping options (continued) pin configuration function
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 69 16. cpu h ardware i nterface and a ddress m apping the gt-482xx can work in both managed and unmanaged implementations. when managed, the gt-482xx inter- faces directly with a 32-bit slave bus. the gt-482xx supports single and burst (up to eight 32-bit word) read/write cpu operations. a single interrupt line is used to indicate interrupt requests to the cpu. 16.1 re g ister and memor y mappin g the gt-482xxs internal registers and sdram are memory mapped. bit 22 in the address is used to specify dram area ("0" - dram) or the internal registers ("1" - internal registers). the gt-482xx sdram can be accessed by the cpu. 16.2 cpu interface modes the gt-482xx provides direct interface to 32-bit cpus listed in table 17. multiple gt-482xx devices can be con- nected to the same cpu bus. table 17: gt-482xx cpu support manuf. cpu support idt r3041 glueless interface in r3041 mode. idt r4640 glueless interface through galileos gt-64011 system controller. use gt mode. idt qed rv4650 rv4700 rv5000 rm5260 rm5270 direct interface through galileos gt-64010a and gt-64120 sys- tem controllers. use gt mode. intel i960 ? jx glueless interface in i960jx mode. intel i960 ? cx/hx requires glue logic to multiplex the address and data buses. use i960jx mode. intel i960 ? rx glueless interface in i960jx mode. intel amd cyrix ibm 80486 requires glue logic to multiplex the address and data buses. must terminate bursts not aligned to quad word (16 bytes) since 80486 uses sub-block burst ordering (use ready/bready pins). use i960jx mode. motorola coldfire 5202 glueless interface in coldfire mode. motorola coldfire 5206 requires glue logic to multiplex the address and data buses. use coldfire mode. ibm powerpc 401 minimal glue logic (if any) as this device is compatible with i960jx protocol. use i960jx mode. - pci bus use gt-64111 which has a simple direct connection to gt-482xx. an application note will be available. use gt mode.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 70 revision 1.2 16.3 cpu interface pin definitions the cpu interface pins change definitions depending on the cpu mode chosen. table 18 shows a summary of how to connect cpu pins to the gt-482xx. 16.4 selectin g the cpu mode the cpu mode is selected at reset via the ras*, cas* and dram we* signals, as shown in table 19. these pins should be pulled the appropriate level by pull-up/down resistors. strapping options not shown are reserved and must not be used. 16.5 gt-482xx base address each gt-482xx in a system has a base address in the memory map. the gt-482xx compares bits 31:27 of the address to its own base address. the gt-482xx will respond only if bits ad[31:27] in the address phase of the cycle are equal to the gt-482xx base address register. table 18: cpu interface pin mappings cpu interface pins/mode definition cpu mode ads* w/r* blast* burstaddr [2:1] ready* rdcen* i960 ? jx ads* w/r* blast* pull up rdyrcv* pull up r3041 wr* rd* burst* addr[3:2] ack* rdcen* gt ads* devrw* cstiming* badr[2:1] ready* badr[0] coldfire ts* rw* size[0] pull up da*[0] pull up table 19: cpu mode selection cpu mode ras* cas* dram we* i960 ? jx 0 0 0 coldfire 0 0 1 r3041 0 1 0 gt 0 1 1 table 20: burst size for different cpu modes cpu mode number of long word reads number of long word writes i960 ? jx 1,2,3,4 1,2,3,4 coldfire 1,4 1,4 r3041 1,4 1 gt 1,2,3,4,5,6,7,8 1,2,3,4,5,6,7,8
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 71 the value of the base address register is set by daddr[4:0] pin strapping at reset. each gt-482xx connected to the same bus in a managed system must have a different base address. 16.6 cpu interface applications the following sections provide gt-482xx waveform information illustrating the read/write single long word and read/write bursts for each of the different cpu modes. 16.6.1 i960 ? jx mode figure 13: i960 write single long word cclk ads_ data 0 add ad[31:0] blast_ rd y rcv* ( read y _ ) wr_ note: the cpu can terminate a burst by assertion of blast.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 72 revision 1.2 figure 14: i960 write burst of four long words figure 15: i960 read single long word cclk ads_ data 0 add ad[31:0] blast_ rd y rcv* ( read y _ ) wr_ d 1 d 2 d 3 note: the time when gt-482xx replies to read request (assertion of ready) is not bounded. cclk ads_ d 0 add ad[31:0] blast_ rd y rcv* ( read y _ ) wr_
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 73 figure 16: i960 read burst of four long words 16.6.2 coldfire (motorola 5202) mode figure 17: coldfire 5202 write single long word cclk ads_ d 0 add ad[31:0] blast_ rd y rcv* ( read y _ ) wr_ d 1 d 2 d 3 cclk ts* ( ads_ ) data 0 add ad[31:0] size[0] ( blast_ ) da[0] ( read y _ ) rw ( wr_ )
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 74 revision 1.2 figure 18: coldfire 5202 write burst of four long words figure 19: coldfire 5202 read single long word cclk data 0 add d 1 d 2 d 3 ts* ( ads_ ) ad[31:0] size[0] ( blast_ ) da[0] ( read y _ ) rw ( wr_ ) cclk d 0 add ts* ( ads_ ) ad[31:0] size[0] ( blast_ ) da[0] ( read y _ ) rw ( wr_ )
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 75 figure 20: coldfire 5202 read burst of four long words 16.6.3 r3041 mode figure 21: r3041 write single long word cclk ts* ( ads_ ) size[0] ( blast_ ) da[0] ( read y _ ) rw ( wr_ ) note: the time when gt-482xx replies to read request (assertion of ready) is not bounded d 0 add ad[31:0] d 1 d 2 d 3 cclk data 0 add wr* ( ads_ ) ad[31:0] rdcen* ack* ( read y _ ) rd* ( wr_ )
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 76 revision 1.2 figure 22: r3041 read single long word figure 23: r3041 read burst of four long words cclk wr* ( ads_ ) d 0 add ad[31:0] rdcen* ack* ( read y _ ) rd* ( wr_ ) cclk d 0 add d 1 d 2 d 3 wr* ( ads_ ) ad[31:0] rdcen* ack* ( read y _ ) rd* ( wr_ ) notes: the time when gt-482xx replies to read request (assertion of ready) is not bounded. on the 3041 writes to gt-482xx is done only at single long word write.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 77 16.6.4 galileo (gt) mode figure 24: gt write single long word figure 25: gt write burst of four long words cclk ads_ data 0 add ad[31:0] cstiming (blast_) ready_ devrw* (rw_) cclk ads_ data 0 add ad[31:0] d 1 cstiming (blast_) ready_ devrw* (rw_) d 2
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 78 revision 1.2 figure 26: gt read single long word figure 27: gt read burst of four long words cclk ads_ d 0 add ad[31:0] cstiming (blast_) ready_ devrw* (rw_) note: the time when gt-482xx replies to read request (assertion of ready) is not bounded. cclk ads_ d 0 add ad[31:0] d 1 d 2 d 3 cstiming (blast_) ready_ devrw* (rw_)
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 79 16.7 cpu interface priorit y cpu access to the gt-482xxs dram is the lowest priority in the dram arbiter. in order to prevent deadlocks, the gt-482xx incorporates a cpu-to-dram access timer. this timer starts counting when the cpu requests an access to the dram. when the timer expires, the cpu will be the next master to access the dram. the timer can be enabled and programed via cpu time out register. 16.8 memor y endianess the gt-482xx treats sdram as a little-endian array. when data is fetched from a 32-bit word for transmission it is fetched in the following sequence: bits [7:0], bits [15:8], bits [23:16], bits [31:24]. the software engineer should keep this in mind when creating/modifying packets within gt-482xx memory.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 80 revision 1.2 17. sdram i nterface the gt-482xx includes all of the logic needed for a glueless interface to 1-4 megabytes of synchronous dram or synchronous graphics ram. (sgram is supported because of the lower density that allows the creation of 1mbyte arrays.) the sdram interface runs at the switching core frequency as determined by aclk. speeds up to 66mhz are supported. refresh is handled automatically by the gt-482xx as well. 17.1 dram confi g uration the user can set the dram refresh time according to table 54, dram configuration, offset: 0x1448, on page 101. the cas and ras parameters can be set as shown in table 55, dram parameters, offset: 0x144c, on page 101. see table 16, reset pin strapping options, on page 66 for dram size sampled at the dqm pin. 17.2 dram initialization the gt-482xx automatically resets all address tables after reset deassertion. for 1 mb dram mode the process takes 50,000 aclk cycles, for 4 mb dram mode the process takes 200,000 aclk cycles. during address table reset the gt-482xx will not accept any incoming packets. the gt-482xx automatically initializes the sdram after reset. this initialization process can be performed by the cpu using the dram configuration registers.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 81 18. r egister t ables the gt-482xx incorporates command registers and various counters for management purposes. the gt-482xx can work in stand-alone mode. in this mode there is no requirement for cpu intervention (a system with no cpu) in which case the default values of the control registers are used. the gt-482xx internal registers have 32-bit accesses. table 21 lists the registers, their offset, read/write attributes and the corresponding tables and page numbers that provide detailed descriptions for each register. these registers must be accessed as single data accesses only (burst accesses are not allowed). table 21: register map table description offset read/write table/page number gt-482xx base address 0x0 r/w table 22 on page 84 global control register 0x4 r/w table 23 on page 84 status register 0x8 read only table 24 on page 87 sniffer + aging timer 0xc r/w table 25 on page 88 serial parameters for 10mbps 0x10 r/w table 26 on page 88 watchdog and tx threshold 0x14 r/w table 28 on page 89 interrupt cause 0x18 r/w table 29 on page 90 interrupt mask 0x1c r/w table 30 on page 91 cpu tx high desc1 0x20 r/w table 31 on page 91 cpu tx high desc2 0x24 r/w table 32 on page 92 cpu tx low desc1 0x28 r/w section 18.1.2 page 93 cpu tx low desc2 0x2c r/w section 18.1.2 page 93 cpu el free req 0x30 r/w table 35 on page 93 cpu empty buffer 0x34 read only table 36 on page 94 cpu enqueue1 0x38 r/w table 37 on page 94 cpu enqueue2 0x3c r/w table 38 on page 94 cpu new address1 0x40 write only table 39 on page 95 cpu new address2 0x44 write only table 40 on page 95 cpu new address3 0x48 r/w table 41 on page 96 cpu query 0x4c read only table 42 on page 96 smi register 0x50 r/w table 43 on page 98 802.1q ethertype 0x54 r/w table 44 on page 98
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 82 revision 1.2 general purpose register1 0x58 r/w table 45 on page 98 general purpose register2 0x5c r/w table 46 on page 99 rx_10 threshold register 0x60 r/w table 47 on page 99 rx_100 threshold register 0x64 r/w table 48 on page 99 cpu threshold register 0x68 r/w table 49 on page 100 led override register 0x6c r/w table 50 on page 100 source address low register 0x70 r/w table 51 on page 100 source address high register 0x74 r/w table 52 on page 101 serial parameters for 100mbps 0x78 r/w table 27 on page 88 cpu time out register 0x7c r/w table 53 on page 101 port control register[3:0] 0x400 - 0x40c r/w table 58 on page 102 ease register[3:0] 0x410 - 0x41c write only table 61 on page 107 port 0 counter 0x600 - 0x654 read only table 63 on page 109 port 1 counter 0x680 - 0x6d4 read only table 63 on page 109 port 2 counter 0x700 - 0x754 read only table 63 on page 109 port 3 counter 0x780 - 0x7d4 read only table 63 on page 109 port control register[7:4] 0x800 - 0x80c r/w table 58 on page 102 ease register[7:4] 0x810 - 0x81c write only table 61 on page 107 port 4 counter 0xa00 - 0xa54 read only table 63 on page 109 port 5 counter 0xa80 - 0xad4 read only table 63 on page 109 port 6 counter 0xb00 - 0xb54 read only table 63 on page 109 port 7 counter 0xb80 - 0xbd4 read only table 63 on page 109 port control register[11:8] 0xc00 - 0xc0c r/w table 58 on page 102 ease register[11:8] 0xc10 - 0xc1c write only table 61 on page 107 port 8 counter 0xe00 - 0xe54 read only table 63 on page 109 port 9 counter 0xe80 - 0xed4 read only table 63 on page 109 port 10 counter 0xf00 - 0xf54 read only table 63 on page 109 port 11 counter 0xf80 - 0xfd4 read only table 63 on page 109 port control register 12 0x1000 r/w table 59 on page 104 port control register 13 0x1004 r/w table 60 on page 106 table 21: register map table (continued) description offset read/write table/page number
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 83 ease register[13:12] 0x1008 - 0x100c write only table 61 on page 107 port 12 counter 0x1200 - 0x1254 read only table 63 on page 109 port 13 counter 0x1280 - 0x12d4 read only table 63 on page 109 dram configuration 0x1448 r/w table 54 on page 101 dram parameters 0x144c r/w table 55 on page 101 sdram operation 0x1474 r/w table 56 on page 102 extramrsbits 0x1478 reserved reserved address decode 0x147c read only table 57 on page 102 table 21: register map table (continued) description offset read/write table/page number
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 84 revision 1.2 18.1 re g ister description table 22: base address, offset: 0x00 bits field name function initial value 31:27 baseaddress device base address daddr[4:0] at reset 26:0 reserved reserved 0x0 table 23: global control, offset: 0x04 bits field name function initial value 0 swreset software reset 1 0 - no effect 1 - reset all internal units except for the cpu unit to their initial state 0x0 1 agingtrigger aging trigger (only valid if 3:2 are written 10). when this bit is changed from low to high, the gt-482xx will scan the address table and age out (remove old addresses) cpu should clear this bit. note: if aging mode is set to trigger mode and this bit is set to 1 and is not cleared, it is equivalent to automatic aging mode. 0x0 3:2 agingmode aging mode: 00 - no aging support 01 - automatic aging 10 - trigger mode 11 - reserved 0x01 4 learning address mac learning mode 0 - mode 0 1 - mode 1 in most applications, this bit does not need to be changed. designers of managed systems may want to experiment with this bit to improve address learn- ing performance. initial value should be 0x1 for p-0/1/2 and 0x0 for p- 3/4. 0x1 for p-0/1/2 0x0 for p-3/4 5 forwunk forward unknown packets. defines whether the gt-482xx will forward unknown packets to the cpu or not. 0 - do not forward to cpu 1 - forward to cpu note: for exact description see "address recogni- tion" on page 28 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 85 6 forwnewadd forward new address. defines whether the gt-482xx will forward new_address messages to the cpu or not. 0 - do not forward 1 - forward 0x0 7 forwaged addr forward aged out address defines whether the gt-482xx forwards new_address messages for aged out addresses to the cpu or not. 0 - do not forward 1 - forward 0x0 8 cpuen cpu enable. this bit indicates that there is a cpu in the system. 0 - cpu does not exist 1 - cpu exists 0x0 11-9 priority weight these bits indicates the priority weight as follows: 000 - one packet is transmitted from the high priority queue, and one packet is transmitted from the low priority queue. 001 - 2 from the high queue, 1 from the low 010 - 4 from the high queue, 1 from the low 011 - 6 from the high queue, 1 from the low 100 - 8 from the high queue, 1 from the low 101 - 10 from the high queue, 1 from the low 110 - 12 from the high queue, 1 from the low 111 - all packets from the high queue. 0x000 12 bufthren buffer threshold enable. 0 - there is no limitation on the buffers allocation (other than physical memory size.) 1 - the buffers allocated to the ports and the cpu are limited to the number which is written in the rx buff- ers threshold register. this bit is meaningful only when disbufthr* pin is disabled. daddr[10] at reset 13 reserved must be written 0 0x0 14 forwmulti forward multicast to cpu only. 0 - the gt-482xx forwards multicast packets to all the ports and to the cpu. 1 - multicast packets forwarded only to the cpu. note: for exact description see "address recogni- tion" on page 28. 0x0 table 23: global control, offset: 0x04 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 86 revision 1.2 15 paren partition enable. when more than 32 collisions occur on a 10mbps port, or more than 60 collisions occur on a 100mbps port while transmitting, the gt-482xx enters the par- tition mode. it waits for the first good packet from the wire, and then goes back to normal mode. under partition mode it continues transmitting, but not receiving. 0 - partition mode disabled 1 - partition mode enabled 0x0 16 spanen spanning tree enable. 0 - the bpdu (bridge protocol data unit) packets are treated as multicast packets, and therefore are forwarded to all ports. 1 - the gt-482xx forwards bpdu packets only to the cpu. 0x0 17 enease ease sampling enable/disable. 0 - ease sampling disabled. 1 - ease sampling enabled. must be set if ease is initialized and any of the ports are enabled. note: bit 8 must be set to 1 (cpu enabled) prior to setting this bit to 1.. 0x0 18 enerrsource errored source address enable/disable. 0 - error source disabled. 1 - error source enabled. 0x0 19 mibctrmode 0 - mib counters reflect forwarded packets only. 1 - mib counters reflect local and forwarded packets. note: a local packet is a packet which is destined to a station on the same port and is not switched. 0x0 20 enabledevice used in conjunction with endev* pin to enable or dis- able the gt-482xx. refer to endev* description for more information. 0x0 21 mibclrmode mib counter clear-on-read mode 0 - mib counters will be cleared after they have been read. 1 - mib counters will not be cleared after they have been read. 0x0 22 igmpen igmp enable 0 - treats igmp packets as multicast and send to all ports 1- send igmp only to the cpu 0x0 table 23: global control, offset: 0x04 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 87 1. on software reset, any register bits that are sampled by configuration pins are not affected. all other register bits are reset to their initial value. 23 crcen crc enable - enable crc generation. 0 - disable 1 - enable 0x0 24 limit4 limit4 - this bit together with limit4 pin selects the number of consecutive collisions which will occur before the collision counter is reset. when the logical or of this bit and limit4 pin is low, 16 consecutive collisions must occur before the collision counter is reset (802.3 standard). when high, 4 consecutive collisions must occur before the collision counter is reset (more aggressive). 0x0 25 syncmode synchronous mode 0 - cclk and aclk are not synchronized 1 - cclk and aclk are synchronized and should be driven from the same clock source note: the gt-482xx can work in asynchronous mode even if the aclk and cclk are the same. 0x0 26 dispktlock discard packet in lock mode 0 - discards the packet with a new address in locked mode 1 - forwards the packet with new address in locked mode 0x0 31:27 reserved - table 24: status register, offset: 0x08 bits field name function initial value 2:0 revision number indicates the gt-482xx revision number 0x0 3 dram_size indicates the dram size: 0 - 1mbyte. 1 - 4mbyte. dqm at reset 17:4 port 13:0 link these bits indicate link on the ports. link on the 10mbps ports (0-11) is indicated by a 0. link on the 100mbps ports (13-12) is indicated by a 1. 0x0 31:18 port 13: 0 partition these bits indicate partition on the ports 0x0 table 23: global control, offset: 0x04 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 88 revision 1.2 table 25: sniffer and aging timer, offset: 0x0c bits field name function initial value 0 sniffen sniffer enable 0 - sniffer mode is disabled 1 - sniffer mode is enabled 0x0 4:1 srcsniff these bits specify the source sniffer channel 0x0 8:5 trgsniff these bits specify the target sniffer channel note : 0xe (14d) specifies the cpu as the target sniffer 0x0 14:9 aging timer these bits specify the value of the aging timer. see "address aging" on page 30 for more information. 0x1e table 26: serial parameters 10 register, offset: 0x10 bits field name function initial value 3-0 jam_length 4 bits to determine the jam_length (in backpressure). the step is 0.8msec. the value of the jam_length can vary between 0.8ms to 12msec 0100b (3.2msec) 10-4 jam_ipg 7 bits to determine the jam_ipg. the step is 100nsec (1 bit time). the jam_ipg vary between 1 bit time to 128. 0010000b (16- bit time) 17-11 ipg_jam_to_dat a 7 bits to determine the ipg jam to data. the step is 100nsec (1 bit time). the jam_ipg vary between 1 bit time to 128. 0011110b ( 30- bit time) 24:18 ipgdata inter-packet gap (ipg) data. the step is 100ns (1 bit-time). the default value is 96 decimal (9.6 m s). note that the ipg during jam varies between 1 bit-time and 128 bit-times. 096d 31:25 datablind data blinder. datablind is the inhibit time. the time the gt-482xx port does not look at the line to decide to transmit.the range is 0 to 96 in 100ns increments. the default is 64 decimal (6.4us). 064d table 27: serial parameters 100 register, offset: 0x78 bits field name function initial value 1:0 jam_length 2 bits to determine the jam_length (in backpressure) as follows: 00 - 2k nibbles 01 - 4k nibbles 10 - 8k nibbles 11 - 10k nibbles 11b (10k nib- bles)
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 89 6:2 jam_ipg 5 bits to determine the jam_ipg. the step is 10nsec (1 bit time). the jam_ipg vary between 1 bit time to 32. 01000b (8 bit time) 11:7 ipg_jam_to_data 5 bits to determine the ipg jam to data. the step is 10nsec (1 bit time). the jam_ipg vary between 1 bit time to 32. 10000b (16 bit time) 16:12 ipgdata inter-packet gap (ipg): the ipg varies between 12 bit- times (0x3) and 124 bit-times (0x1f). the step is 40ns@100mbs or 400 ns@10mbs (4 bit-times). the default value is 18 hex, or 0.96us@100mbs (9.6us@10mbs). value should be written in hexadecimal format. note : these bits may be changed only when porten bits are set to 0 in all port control registers (port is disabled). 0x18 = 24 deci- mal 21:17 datablind data blinder: the number of nibbles from the beginning of the ifg, in which the gt-482xx will restart the ifg counter when detecting a carrier activity. following this value, the gt- 482xx will enter the data blinder zone and will not reset the ifg counter to ensure fair access to the medium. value should be written in hexadecimal format. the default is 10 hex (64 bit times - 2/3 of the default ifg). the step is 40ns (4 bit-times). valid range is 3 to 1f hex nibbles. note : these bits may be changed only when porten bits are set to 0 in all port control registers (port is disabled). 0x10 = 16 deci- mal 25:22 reserved reserved 0x0 table 28: watchdog and tx threshold register, offset: 0x14 bits field name function initial value 3:0 txwattim tx watchdog timer. for 100 mbps operation, the default value of the timer is 63msec and the range is between 10.5msec and 168msec, in 10.5 ms steps. for 10 mbps operation, the default value of the timer is 630msec and the range is between 105ms to 1680ms, in 105 ms steps. valid val- ues: 1 to f hex. value should be written in hexadecimal format. 0x6 (63 ms @ 100mbps; 630 ms @ 10 mbps) 8:4 chainnu chain number. these bits specify the number of entries in a chain in the address table 0x08 (16 entries) table 27: serial parameters 100 register, offset: 0x78 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 90 revision 1.2 11:9 txquethr transmit queue threshold these bits determine the threshold of the transmit queue. when the transmit queue exceeds this limit, a packet that destined to this queue will be discarded. 000: threshold is 64 in 1m, 256 in 4m 001: threshold is 128 in 1m, 512 in 4m 010: threshold is 192 in 1m, 768 in 4m 011: threshold is 256 in 1m, 1024 in 4m 100: threshold is 320 in 1m, 1280 in 4m 101: threshold is 384 in 1m, 1536 in 4m 110: threshold is 448 in 1m, 1792 in 4m 111: threshold is 512 in 1m, 2048 in 4m 0x3 table 29: interrupt cause, offset: 0x18 bits field name function initial value 0 intsumm interrupt summary. logical or of all the interrupt bits and their mask. intsumm is exactly the inverse polarity of int* pin. 0x0 1 txdesch this bit is set by the gt-482xx upon loading the cpu tx high priority desc register 0x0 2 txdescl this bit is set by the gt-482xx upon loading the cpu tx low priority desc register 0x0 3 emptybuff this bit is set by the gt-482xx upon loading the cpu empty list register 0x0 4 query this bit is set by the gt-482xx upon loading the query register 0x0 5 addrrecf address recognition failed. this bit is set by the gt-482xx when the address recog- nition cycle fails (due to a large number of mac addresses). 0x0 6 flushtxq flush tx queue. this bit is set by the gt-482xx when one of the tx queues is flushed due to the watchdog timer. 0x0 7 linkchange link state change. this bit is set by the gt-482xx upon a change in the link state (down->up, up->down) for any port. 0x0 8 part partition. this bit is set by the gt-482xx upon entering partition state in one of the ports. 0x0 22:9 easeregister ease_register of port 13 to 0 has reached terminal count of 0 0x0 table 28: watchdog and tx threshold register, offset: 0x14 bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 91 note: clearing an interrupt cause bit is done by writing 0 value to it. writing 1 has no effect. 18.1.1 cpu tx high desc1 and 2, offset: 0x20, 0x24 tx high desc1 and tx high desc2 registers contain one of the following two formats depending on desctype bit [30] in the cpu tx high desc2: ? cpu_tx_high_desc2[30] = 0 - packet descriptor ? cpu_tx_high_desc2[30] = 1 - new_address message (can be new_address, error_source address or an address that was removed due to automatic aging. note: these two registers are not burst read. 1. note that all interrupts are unmasked by default. 23 errorsasent error_source message sent to cpu 0x0 table 30: interrupt mask 1 , offset: 0x1c bits field name function initial value 23:1 maskbits mask to the cpu interrupt line for the appropriate bits in the interrupt cause register. 0 value enables the interrupt for the corresponding cause bit. 0x0 table 31: cpu tx high desc1 - packet descriptor, offset 0x20 bits field name function initial value 10:0 sourbufaddr source buffer address (divided by 0x600) 0x0 21:11 byte count byte count 0x0 25:22 sourceport source port number 0x0 26 mult multicast packet (1 - multicast) 0x0 27 unk unknown packet (1 - uknown) 0x0 28 sniff sniffer packet (1 - sniffer) 0x0 29 igmp igmp packet (1 - igmp) 0x0 30 interv intervention packet (1 - intervention) 0x0 31 reserved reserved 0x0 table 29: interrupt cause, offset: 0x18 bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 92 revision 1.2 table 32: cpu tx high desc2 - packet descriptor, offset 0x24 bits field name function initial value 13:0 easesamp ease sampling for ports [13:0] 0 - ease sampling is enabled for port 1 - ease sampling is disabled for port 0x0 14 easesampcpu ease sample is an original packet to cpu 0 - ease sample is an original packet to cpu 1 - ease sample is not an original packet to cpu 0x0 29:15 - reserved 0x0 30 desctype descriptor type 0 - packet descriptor 1 - new_address message 0x0 31 valid valid bit. 0 - cpu tx high1 and 2 do not contain valid data 1 - cpu tx high1 and 2 contain valid data. valid bit is cleared upon reading cpu tx high desc2. 0x0 table 33: cpu tx high desc1 - new address, offset 0x20 bits field name function initial value 31:0 macaddr[16:47] mac address[16:47] 0x0 table 34: cpu tx high desc2 - new address, offset 0x24 bits field name function initial value 15:0 macaddr mac address[0:15] 0x0 19:16 sourceport source port number 0x0 20 fcserr fcs error indication (only for error source) 0x0 21 overcount over count frame indication (only for error source) 0x0 22 pd priority destination 0x0 23 ps priority source 0x0 24 st static 0x0 25 mult multiple 0x0 26 id intervention destination 0x0 27 is intervention source 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 93 18.1.2 cpu tx low desc1 and 2, offset: 0x28, 0x2c tx low desc1 and tx low desc2 registers have the same format as the cpu tx high desc registers. the new_ address messages are always entered into the high descriptor, therefore the cpu tx low desc2 register contains only packet_descriptor messages (cpu tx low desc2[30] = 0). . , , , , , , , , , , 29:28 natype new address type: 00: new address 01: error source address 10: address that was removed from the address table due to aging 11: reserved 30 desctype descriptor type 0 - packet descriptor 1 - new_address message 31 valid valid bit. 0 - cpu tx high1 and 2 do not contain valid data 1 - cpu tx high1 and 2 contain valid data. valid bit is cleared upon reading cpu tx high desc2. table 35: cpu el free req, offset: 0x30 bits field name function initial value 10:0 sourbufaddr source buffer address (divided by 0x600) 0x0 14:11 sourceport source port number 0x0 18:15 trgport target port number 0x0 19 mult multicast packet (1 - multicast) note : the value of this bit must match the value of the mult bit (bit 26) in the cpu tx high desc1 (offset 0x20). 0x0 30:20 reserved reserved reserved 31 busy busy bit 0 - not busy, the cpu can re-load this register 1 - busy - the data in this register was not processed. the cpu should not re-load this register. when the cpu writes this register to clear a buffer, it should write this bit as 1. before the cpu proceeds to clear another buffer, it should poll this bit until it has a value of 0. 0x0 table 34: cpu tx high desc2 - new address, offset 0x24 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 94 revision 1.2 table 36: cpu empty buffer, offset: 0x34 bits field name function initial value 10:0 buffaddr buffer address (divided by 0x600) 0x0 30:11 reserved reserved reserved 31 valid valid bit. 0 - the address (pointer) in 10:0 is not valid. 1 - this register contains a valid address (pointer) to an empty buffer in 10:0. this bit is set to 0 upon reading this register. 0x0 table 37: cpu enqueue1, offset: 0x38 bits field name function initial value 10:0 trgbufaddr target buffer address (divided by 0x600) 0x0 21:11 byte count byte count. when gencrc is set, byte count does not include the 4 bytes of crc 0x0 22 mult multicast packet (1 - multicast, 0 - unicast) note : should comply with the limitations set forth in sec- tion 7.3 "forwarding a packet to the cpu" on page 33 with respect to re-enqueuing of packets. 0x0 23 pri priority 0 - low priority 1 - high priority 0x0 24 gencrc crc generation 0 - do not generate crc on transmit 1 - generate crc on transmit note: bit 23, crcen, of the global control register (0x04) must be set to 1 in order to generate crc on transmit. 0x0 31:25 reserved reserved 0x0 table 38: cpu enqueue2, offset: 0x3c bits field name function initial value 13:0 tgtportbitmap target port bitmap (one bit per port, this field is ignored when queuing a unicast packet) 0x0 15:14 reserved reserved 0x0 19:16 tgtport target port number (this field is ignored when queuing a multicast packet) 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 95 23:20 srcport source port number (0xe if source port is cpu) 0x0 30:24 reserved reserved 0x0 31 busy busy bit 0 - not busy, the cpu can re-load this register 1 - busy - the data in this register was not processed. the cpu should not re-load this register. when the cpu writes this register to queue a transmit packet, it should write this bit as 1. before the cpu pro- ceeds to enqueue another buffer, it should poll this bit until it has a value of 0. note: the busy bit applies to both cpu enqueue regis- ters at offsets 0x38 and 0x3c. 0x0 table 39: cpu new address1, offset: 0x40 bits field name function initial value 0 natype new address type 0 - cpu is writing a new address to the table or is updat- ing a current entry in the address table 1 - the cpu is querying the address table for a particular entry. when querying, the only relevant fields are mac[47:20] and mac[19:0]. the rest of the fields in newaddress1, newaddress2 and newaddress3 are ignored. 0x0 1 sk skip entry 0 - no not remove this entry from the address table 1 - remove this entry from the address table 0x0 2 aging aging 0 - new address 1 - not new address 0x0 3 reserved reserved 0x0 31:4 mac[47:20] mac[47:20] 0x0 table 40: cpu new address2, offset: 0x44 bits field name function initial value 19:0 mac[19:0] mac[19:0] 0x0 23:20 portnu port number 0x0 table 38: cpu enqueue2, offset: 0x3c bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 96 revision 1.2 24 pd priority destination 0 - low 1 - high 0x0 25 ps priority source 0 - low 1 - high 0x0 26 st static 0 - learn address every time it comes in on different port 1 - do not learn address every time it comes in on differ- ent port 0x0 27 mult multiple (only valid if static is 1) 0 - do not send to multiple ports on static address 1 -send on multiple ports to static address 0x0 28 id intervention destination 0 - intervention on destination address not set 1 - intervention on destination address is set 0x0 29 is intervention source 0 - intervention on source address is not set 1 - intervention on source address is set 0x0 31:30 reserved reserved 0x0 table 41: cpu new address3, offset: 0x48 bits field name function initial value 14:0 forw forwarding bits for ports [13:0] and the cpu (#14) 0x0 30:15 reserved reserved 0x0 31 busy busy bit 0 - not busy, the cpu can re-load this register 1 - busy - the data in this register was not processed. the cpu should not re-load this register. busy bit is set to 1 by the cpu and cleared when the gt- 482xx takes the data. note: the busy bit applies to all three cpu new address registers at offsets 0x40, 0x44, and 0x48. 0x0 table 42: cpu query, offset: 0x4c bits field name function initial value 0 reserved reserved 0x0 table 40: cpu new address2, offset: 0x44 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 97 1 entryvalid entry valid - this bit indicates if the address was found: 0 - was not found 1 - was found 0x0 2 pd priority destination 0 - low priority 1 - high priority 0x0 3 ps priority source 0 - low priority 1 - high priority 0x0 7:4 sourceport source port number 0x0 8 aging aging 0 - new address 1 - not new address & will be cleared 0x0 9 st static 0 - learn address every time it comes in on dif- ferent port 1 - do not learn address every time it comes in on different port 0x0 10 mult multiple (only valid if static is 1) 0 - do not send to multiple ports on static address 1 -send on multiple ports to static address 0x0 11 id intervention destination 0 - intervention on destination address not set 1 - intervention on destination address is set 0x0 12 is intervention source 0 - intervention on source address not set 1 - intervention on source address is set 0x0 27:13 forw forwarding bits for ports [13:0] and the cpu (#14) 0x0 30:28 reserved reserved reserved 31 valid valid bit. 0 - cpu query does not contain valid data 1 - cpu query contains valid data. valid bit is cleared upon reading this register 0x0 table 42: cpu query, offset: 0x4c bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 98 revision 1.2 1. note: for compliance with ieee standards 802.1p and 802.1q this register should be programmed to 0x8100 for p3/p4. table 43: smi register, offset: 0x50 bits field name function initial value 15:0 data for smi read operation: two cpu transactions are required: (1) cpu write to the smi register with opcode = 1, phyad, regad with the data being any value. (2) cpu read from the smi register. when read- ing back the smi register, the data is the addressed phy register contents if the readvalid bit (#27) is 1. the data remains undefined as long as readvalid is 0. for smi write operation: one cpu transaction is required: cpu write to the smi register with opcode = 0, phyad, regad with the data to be written to the addressed phy register. n/a 20:16 phyad phy device address 0x0 25:21 regad phy device register address 0x0 26 opcode 0 - write 1 - read 0x0 27 readvalid 1 - indicates that the read operation has been com- pleted for the addressed regad register, and the data is valid on the data field. 0x0 28 busy busy bit 0 - not busy, the cpu can re-load this register 1 - busy - the data in this register was not processed. the cpu should not re-load this register. busy bit is set to 1 by the cpu and cleared when the data was written to the phy registers. 0x0 31:29 n/a this bits should be driven 0x0 during any write to the smi register. 0x0 table 44: 802.1q ethertype register, offset: 0x54 bits field name function initial value 15:0 vlethertype vl ethertype value 0x0 - p0/p1/p2 0x8100 - p3/p4 1 table 45: general purpose register1, offset: 0x58 bits field name function initial value 11:0 gp general purpose value - these pins are used to sample or to drive the cole/gp[11:0] pins in 10base-t or 10base-fl modes. 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 99 table 46: general purpose register2, offset: 0x5c bits field name function initial value 11:0 gpdir general purpose direction. these bits determine the direc- tion of the cole/gp[11:0] pins (per bit basis) as follows: 1 - cole/gp[11:0] are inputs. gp bits reflect the value on these pins. 0 - cole/gp[11:0] are output. they carry the value of gp bits. 0xfff table 47: rx_10 threshold, offset: 0x60 bits field name function initial value 7:0 rxbufthr receive buffer threshold for the 10mbps ports. the thresh- old is: rxbufthr * 8. 0x4 @1m (32) 0x8 @4m (64) earlier ver- sions: 0x2 @1m (16) for gt-48212- p5: 0x3 (32) 15:8 xofflimit x-off limit - when flow control is enabled, the gt-482xx will send x-off packet when the number of buffers for this port reach (xofflimit * 4) value 0x7 @1m (28) 0x8 @4m (32) 23:16 xonlimit x-on limit - when flow control is enabled, the gt-482xx will send x-on packet when the number of buffers for this port going below (xonlimit * 4) value 0x6 @1m (24) 0x6 @4m (24) 31:24 hollimit hol limit - the gt-482xx discards packet when the tx queue exceeds txthr limit and the number of buffers allo- cated to this port exceed (hollimit * 8) 0x3 @1m (24) 0x3@4m (24) table 48: rx_100 threshold, offset: 0x64 bits field name function initial value 7:0 rxbufthr receive buffer threshold for the 100mbps ports. the threshold is: rxbufthr * 8. 0x8 @1m (64) 0x4a @4m (592) earlier versions: 0x12 @1m (144) for gt-48212- p5: 0x8 (64) 15:8 xofflimit x-off limit - when flow control is enabled, the gt-482xx will send x-off packet when the number of buffers for this port reach (xofflimit * 8) value 0x3 @1m (24) 0x46 @4m (560)
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 100 revision 1.2 23:16 xonlimit x-on limit - when flow control is enabled, the gt-482xx will send x-on packet when the number of buffers for this port going below (xonlimit * 8) value 0x3 @1m (24) 0x43 @4m (536) 31:24 hollimit hol limit - the gt-482xx discards packet when the tx queue exceeds txthr limit and the number of buffers allo- cated to this port exceed (hollimit * 8) 0x7 @1m (56) 0x43 @4m (536) table 49: cpu threshold, offset: 0x68 bits field name function initial value 7:0 cpubufthr buffer threshold for the cpu. the threshold is: cpubufthr * 8. 0x2 @1m 0x8 @4m table 50: led override, offset: 0x6c bits field name function initial value 13:0 leddata led data bits 0x0 14 override override - this bit selects the data to be driven on the led- data pin in ledmode1 0 - bits #0 to #27 of leddata contain link_test_pass indica- tion 1 - bits #0 and #1 contain leddata[0] bits #2 and #3 contain leddata[1] * * bits #26 and #27 contain leddata[13] 0x0 table 51: flow control source address low, offset: 0x70 bits field name function initial value 31:0 sa[16:47] source address - the most significant bits of the source address for all ports. this address is being used for flow control. note: sa[47] is the i/g bit. the first bit to be received from the wire. 0x0 table 48: rx_100 threshold, offset: 0x64 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 101 table 52: flow control source address high, offset: 0x74 bits field name function initial value 11:0 sa[4:15] source address - the most significant bits of the source address for all ports. this address is being used for flow control. 0x0 table 53: cpu time out register, offset: 0x7c bits field name function initial value 15:0 cputimeout cpu time out - these bits specify the initial value in aclk cycles of the cpu to dram access timer 0x0 16 timeouten timeout en - enable the cpu to dram access timer. 0 - disable 1 - enable 0x0 table 54: dram configuration, offset: 0x1448 bits field name function initial value 13:0 refcntint refresh counter initial value 0x200 (10 micro seconds @50mhz) table 55: dram parameters, offset: 0x144c bits field name function initial value 1:0 caslat cas latency 00 - reserved 01 - 2 cycles 10 - 3 cycles 11 - reser ved 0x01 3 raspretime ras precharge time 0 - 1 clocks 1 - 2 clocks 0x0 10 rastocas ras to cas cycles 0 - 2 clocks 1 - 3 clocks 0x0 12 burstlimit burst limit 0 - 8 words 1 - 4 words 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 102 revision 1.2 table 56: sdram operation, offset: 0x1474 bits field name function initial value 2:0 sdramop sdram operation. these bits select the sdram opera- tion as follows: 000 - normal dram mode 001 - nop command 010 - all banks precharge command 011 - mode register command enable 100 - cbr cycle enable 0x0 table 57: address decode, offset: 0x147c bits field name function initial value 0 dram size 0 - 1mbyte 1 - 4mbyte dqm pin at reset table 58: port control (10m ports), offset: 0x400-0x40c, 0x800 - 0x80c, 0xc00 - 0xc0c bits field name function initial value 0 porten port enable. 0 - port is disabled 1 - port is enabled 0x1 1 fulldx half/full duplex. 0 - port works in half-duplex mode 1 - port works in full-duplex mode txde (at reset) 3:2 sermode serial mode. these bits indicate the serial mode. the logic order at reset is ddata[1:0] for port 0, ddata[3:2] for port 1, where port n corresponds to ddata [ 2 n +1:2 n ] . 00 - 10base-t 01 - 10base-fl 10 - aui 11 - reserved corresponding ddata[] pins at reset (see table 16, reset pin strapping options, on page 66) 4 lockport locked port 0 - port is in normal mode 1 - port is locked. the gt-482xx does not learns new addresses and send then only to the cpu 0x0 5 forbroadcpu forward broadcast to the cpu. meaningful only when fil- broad (bit 10) is clear. 0 - forward broadcast packets to all ports 1 - forward broadcast packets only to the cpu note: for exact description see "address recognition" on page 28 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 103 6 backpressureen back pressure enable. only valid when fulldx (bit 1) is set to 0. 0 - disable 1 - enable daddr[11] at reset 7 flowcontrolen flow control enable. only valid when fulldx (bit 1) is set to 1. 0 - disable 1 - enable ddata[28] at reset 8 easeen enable ease on specific port. 0 -enable 1- disable 0x0 9 prio priority 0 - low priority 1 - high priority 0x0 10 filbroad filter broadcast. 0 - broadcast packets are forwarded to all ports. 1 - the gt-482xx discards broadcast packets. note: for exact description see "address recognition" on page 28 0x0 11 forwunk enable forwarding unknown unicast da packets to this transmit port. 0 - unknown packets are forwarded. 1 - the gt-482xx does not forward unknown packets to this port. note: for exact description see "address recognition" on page 28 0x0 12 spanen spanning tree enable. meaningful only when spanen bit in the global control register is set. 0 - all packets are accepted. 1 - the gt-482xx discards all incoming/outgoing packets except for bpdu packets. 0x0 13 vtagen virtual lan tagging packet extension enable 0 - accept packets up to 1518 bytes in length 1 - accept packets up to 1536 bytes in length daddr[8] at reset 14 forcepri force priority. 0 - priority is set base on the pd, ps, pri bit in the port control register or the 802.1q quality of service feild. 1 - priority is set only based on pri bit in the port control register 0x0 18:15 sa[0:3] source address - the least significant bits of the source address for all ports. this address is being used for flow control. port # table 58: port control (10m ports), offset: 0x400-0x40c, 0x800 - 0x80c, 0xc00 - 0xc0c (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 104 revision 1.2 31:19 reserved table 59: port control 12 (100m ports), offset: 0x1000 bits field name function initial value 0 porten port enable. 0 - port is disabled 1 - port is enabled 0x1 1 fulldx half/full duplex. 0 - port works in half-duplex mode 1 - port works in full-duplex mode daddr[24] for port 12 or daddr[25] for port 13 at reset 2 easeen port12 enable ease on port 12 0 - disabled 1 - enabled 0x0 3 easeen port13 enable ease on port 13 0 - disabled 1 - enabled 0x0 4 lockport locked port 0 - port is in normal mode 1 - port is locked. the gt-482xx does not learns new addresses and send then only to the cpu 0x0 5 forbroadcpu forward broadcast to the cpu. meaningful only when filbroad is clear. 0 - forward broadcast packets to all ports 1 - forward broadcast packets only to the cpu note: for exact description see "address recognition" on page 28 0x0 6 backpressureen back pressure enable 0 - disable 1 - enable daddr[11] at reset 7 flowcontrolen flow control enable 0 - disable 1 - enable ddata[30] for port 13, ddata[29] for port 12 at reset table 58: port control (10m ports), offset: 0x400-0x40c, 0x800 - 0x80c, 0xc00 - 0xc0c (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 105 8 autoneg auto-negotiation enable 0 - auto-negotiation is disable 1 - auto-negotiation is enable ddata[27] for port 13, ddata[26] for port 12 at reset 9 pri priority 0 - low priority. 1 - high priority 0x0 10 filbroad filter broadcast. 0 - broadcast packets are forwarded to all ports. 1 - the the gt-482xx discards broadcast packets. note: for exact description see "address recognition" on page 28 0x0 11 forwunk enable forwarding unknown unicast da packets to this transmit port. 0 - unknown packets are forwarded. 1 - the gt-482xx does not forward unknown packets to this port. note: for exact description see "address recognition" on page 28 0x0 12 spanen spanning tree enable. meaningful only when spanen bit in the global control register is set. 0 - all packets are accepted. 1 - the the gt-482xx discards all incoming/outgoing packets except for bpdu packets. 0x0 13 vtagen virtual lan tagging packet extension enable 0 - accept packets up to 1518 bytes in length 1 - accept packets up to 1536 bytes in length daddr[8] at reset 14 forcepri force priority. 0 - priority is set base on the pd, ps, pri bit in the port control register or the 802.1q quality of service feild. 1 - priority is set based on pri bit in the port control reg- ister 0x0 18:15 sa[0:3] source address - the least significant bits of the source address for all ports. this address is being used for flow control. port # 31:19 reserved table 59: port control 12 (100m ports), offset: 0x1000 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 106 revision 1.2 table 60: port control 13 (100m ports), offset: 0x1004 bits field name function initial value 0 porten port enable. 0 - port is disabled 1 - port is enabled 0x1 1 fulldx half/full duplex. 0 - port works in half-duplex mode 1 - port works in full-duplex mode daddr[24] for port 12 or daddr[25] for port 13 at reset 3:2 port13 expansion priority bit [2] rx_prio: 0 - disabled 1 - enabled bit [3] tx_prio: 0 - disabled 1 - enabled both bits value are sampled at reset as per the inverted value of burst- addr[1] configuration input 4 lockport locked port 0 - port is in normal mode 1 - port is locked. the gt-482xx does not learns new addresses and send then only to the cpu 0x0 5 forbroadcpu forward broadcast to the cpu. meaningful only when filbroad is clear. 0 - forward broadcast packets to all ports 1 - forward broadcast packets only to the cpu note: for exact description see "address recognition" on page 28 0x0 6 backpressureen back pressure enable 0 - disable 1 - enable daddr[11] at reset 7 flowcontrolen flow control enable 0 - disable 1 - enable ddata[30] for port 13, ddata[29] for port 12 at reset 8 autoneg auto-negotiation enable 0 - auto-negotiation is disable 1 - auto-negotiation is enable ddata[27] for port 13, ddata[26] for port 12 at reset 9 pri priority 0 - low priority. 1 - high priority 0x0
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 107 18.2 port mib counters (14 blocks), offset (start): 0x600, 0xa00, 0xe00, 0x1200 the cpu must read all of the mib counters during initialization in order to reset the counters to 0. all counters are 32-bits. the cpu must access the counters using single datum transactions (burst reads/writes are not allowed). 10 filbroad filter broadcast. 0 - broadcast packets are forwarded to all ports. 1 - the the gt-482xx discards broadcast packets. note: for exact description see "address recognition" on page 28 0x0 11 forwunk enable forwarding unknown unicast da packets to this transmit port. 0 - unknown packets are forwarded. 1 - the gt-482xx does not forward unknown packets to this port. note: for exact description see "address recognition" on page 28 0x0 12 spanen spanning tree enable. meaningful only when spanen bit in the global control register is set. 0 - all packets are accepted. 1 - the the gt-482xx discards all incoming/outgoing packets except for bpdu packets. 0x0 13 vtagen virtual lan tagging packet extension enable 0 - accept packets up to 1518 bytes in length 1 - accept packets up to 1536 bytes in length daddr[8] at reset 14 forcepri force priority. 0 - priority is set base on the pd, ps, pri bit in the port control register or the 802.1q quality of service feild. 1 - priority is set based on pri bit in the port control reg- ister 0x0 18:15 sa[0:3] source address - the least significant bits of the source address for all ports. this address is being used for flow control. port # 31:19 reserved table 61: ease register, offset: 0x410-0x41c, 0x810-0x81c,0xc10-0xc1c,0x1008-0x100c bits field name function initial value 19:0 ease_register value loaded to the internal count-down counter of the ports 0x0 31:20 reserved reserved reserved table 60: port control 13 (100m ports), offset: 0x1004 (continued) bits field name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 108 revision 1.2 mib counters can be cleared by reading, or left intact after a read based on the mib clear mode (bit 21 in the glo- bal command register.) during initialization, the cpu must read all of the mib counters in order to reset the counters to 0. the counters will only be reset to 0 if mibclrmode (bit 21 of the global control register) is set to 0 (default). if mibclrmode bit is 1, reading the mib counters will have no effect. table 62 lists the definitions for terms used in the counter descriptions. table 62: definitions used in counter descriptions term definition packet data section all data bytes in the packet following the sfd until the end of the packet packet data length the number of data bytes in the packet data section data octet a single byte from the packet data section nibble 4 bits (half byte) of a data octet misaligned packet a packet with an odd number of nibbles received good packet a received packet which is not rejected and enters the switching core to be transmit- ted later transmitted good packet any transmitted packet from the gt-482xx collision event a collision has been detected until than 576 bit times into the transmitted packet after txen. late collision event a collision has been detected later than 576 bit times into the transmitted packet after txen. rx error event the input rx_err has been asserted dropped packet a received packet which is ignored due to lack of available receive buffers (port is in buffer_full state) local packet a received packet whose destination address is mapped to the receiving port rejected packet a received packet which is not forwarded due to error such as bad crc, rx error event, invalid size (too short or too long). mibctrmode bit 26, mibctrmode, of the global control register (offset 0x140028) vtagen bit 9, vtagen, of the port control register (offset 0x040200-0x040204) maxframesize 1518 for vtagen = 0 (default) or 1536 for vtagen = 1
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 109 table 63: port mib counters address for port 0 counter name function initial value 0x000600 bytes received mibctrmode = 0: this counter is incremented once for every data octet of good packets (unicast + multicast + broadcast) received. mibctrmode = 1: this counter is incremented once for every data octet of good packets (unicast + multicast + broadcast packets) and for local and dropped packets. - 0x000604 bytes sent this counter is incremented once for every data octet of a trans- mitted good packet. - 0x000608 frames received mibctrmode = 0: this counter is incremented once for every good packet (unicast + multicast + broadcast) received. mibctrmode = 1: this counter is incremented once for every good packet (unicast + multicast + broadcast packets) and for local and dropped packets received. - 0x00060c frames sent this counter is incremented once for every transmitted good packet. - 0x000610 total bytes received this counter is incremented once for every data octet of all received packets. this includes data octets of rejected and local packets which are not forwarded to the switching core for transmission. this counter should reflect all the data octets received on the line. note: a nibble is not counted as a whole byte. - 0x000614 total frames received this counter is incremented once for every received packets. this includes rejected and local packets which are not for- warded to the switching core for transmission. this counter should reflect all packets received on the line. - 0x000618 broadcast frames received mibctrmode = 0: this counter is incremented once for every good broadcast packet received. mibctrmode = 1: this counter is incremented once for every good broadcast packet received and for local and dropped broadcast packets. - 0x00061c multicast frames received mibctrmode = 0: this counter is incremented once for every good multicast packet received. mibctrmode = 1: this counter is incremented once for every good multicast packet received and for local and dropped broadcast packets. this counter does not include broadcast packets. -
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 110 revision 1.2 0x000620 crc error this counter is incremented once for every received packet which meets all the following conditions (i.e. logical and of the following conditions): 1. packet data length is between 64 and maxframesize bytes inclusive (i.e. valid packet data length per ieee std). 2. packet has invalid crc (non-a also counted packets with odd number of nibbles). 3. collision event has not been detected. 4. late collision event has not been detected. 5. rx error event has not been detected. - 0x000624 oversize frames this counter is incremented once for every received packet which meets all the following conditions (i.e. logical and of the following conditions): 1. packet data length is greater than and maxframesize. 2. packet has valid crc. 3. rx error event has not been detected. - 0x000628 fragments this counter is incremented once for every received packet which meets all the following conditions (i.e. logical and of the following conditions): 1. packet data length is less than 64 bytes -or- packet without sfd and is less than 64 bytes in length. 2. collision event has not been detected. 3. late collision event has not been detected. 4. rx error event has not been detected. - 0x00062c jabber this counter is incremented once for every received packet which meets all the following conditions (i.e. logical and of the following conditions): 1. packet data length is greater than maxframesize. 2. packet has invalid crc. 3. rx error event has not been detected. - 0x000630 collision this counter is incremented once for every received packet which meets both of the following conditions (i.e. logical and of the following conditions): 1. collision event has been detected. 2. rx error event has not been detected. - 0x000634 late collision this counter is incremented once for every received packet which meets both of the following conditions (i.e. logical and of the following conditions): 1. late collision event has been detected. 2. rx error event has not been detected. - 0x000638 frames 64 bytes this counter is incremented once for every received and trans- mitted packet with size of 64 bytes. this counter includes local, dropped and transmitted packets. - table 63: port mib counters (continued) address for port 0 counter name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 111 0x00063c frames 65-127 bytes this counter is incremented once for every received and trans- mitted packet with size of 65 to 127 bytes. this counter includes local, dropped and transmitted packets. - 0x000640 frames 128-255 bytes this counter is incremented once for every received and trans- mitted packet with size of 128 to 255 bytes. this counter includes local, dropped and transmitted packets. - 0x000644 frames 256-511 bytes this counter is incremented once for every received and trans- mitted packet with size of 256-511 bytes. this counter includes local, dropped and transmitted packets. - 0x000648 frames 512-1023 bytes this counter is incremented once for every received and trans- mitted packet with size of 512-1023 bytes. this counter includes local, dropped and transmitted packets. - 0x00064c frames 1024- 1522 bytes this counter is incremented once for every received and trans- mitted packet with size of 1024 to maxframesize bytes. this counter includes local, dropped and transmitted packets. - 0x000650 mac rx error this counter is incremented once for every received and trans- mitted packet where the rx error event has been detected. the counters that will not be incremented when this counter is incre- mented include: crc error, oversize frames, fragments, jab- ber, collision and late collision. this counter is reserved for ports 0 thru 11. - 0x000654 dropped frames this counter is incremented once for every received packet that is dropped. - table 63: port mib counters (continued) address for port 0 counter name function initial value
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 112 revision 1.2 19. gt-482 xx p inout d ifferences currently all members of the galaxy switch family are supersocket compatible. this means that a properly designed system can accept a GT-48207 (unmanaged 8+2), a gt-48208 (managed 8+2) or a gt-48212 (man- aged 12+2). this section describes how to design such a system. 19.1 pinout differences between GT-48207, gt-48208, and gt-48212 devices the pinout differences between the three galaxy devices are summarized in table 64. 19.2 usin g a gt-48212 in a gt-48208/7 socket: disablin g unused ethernet ports the gt-48208 and GT-48207 do not implement ethernet port numbers 1, 5, 7 and 11 that are found on the gt- 48212. in gt-48208/7 silicon these ports do not exist so no special tying off is required. however, if you need to use a gt-48212 in a gt-48208/7 socket (using only 8 of the 12 ports) then you must properly disable these ports. simply following the attached pinout for the gt-48208/7 will disable these ports if a gt-48212 is placed in the same socket. the pins that are used for receive data for the ports not implemented on the GT-48207/8 (rxde1,5,7,11) are shown as vcc (pins 29, 31, 46, and 50). this disables these ports and prevents accidental clocking when using a gt-48212 in a gt-48208/7 design. if you wish to build a system that can implement either 12 or 8 ethernet ports in the same socket, be sure to pull these pins high through a resistor or jumper. that way you can make it a stuffing option to disable the 4 addi- tional ports or to implement them when a gt-48212 is installed. note: the attached pinout for the gt-48208/7 is updated from previous documentation to reflect the tying off of rxde1/5/7/11. this is the final pinout. 19.3 usin g a gt-48212 or gt-48208 in a GT-48207 socket: disablin g unused cpu interface a similar situation exists with regards to the cpu interface when using a gt-48212/08 in a GT-48207 socket. since the GT-48207 does not implement this interface, if you wish to use a gt-48208/212 in a GT-48207 socket then you must properly disable the cpu interface. simply following the attached pinout for the GT-48207 will dis- able the cpu interface if a gt-48208/212 is placed in the GT-48207 socket. table 64: pinout differences galaxy device functions not implemented pins deleted note gt-48212 n/a n/a baseline pinout gt-48208 ethernet ports 1, 5, 7 and 11 all pins relating to these ports for a gt-48212 to be used in a gt- 48208 socket you must properly dis- able the four unused ethernet ports as described below. GT-48207 ethernet ports 1, 5, 7 and 11 management cpu interface all pins relating to the these ethernet ports and the cpu interface for a gt-48212 to be used in a gt- 48207 socket you must properly dis- able the four unused ethernet ports and disable the cpu interface.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 113 if you wish to build a system that can accept either managed or unmanaged galaxy devices in the same socket, be sure to pull the cpu interface pins high through a resistor or jumper. that way you can make it a stuffing option to disable the cpu interface or to implement it when a gt-48208/212 is installed. 19.4 cclk in an unmana g ed s y stem the cpu clock (cclk) must have a clock source applied in any galaxy system even when no cpu is present (this is also true for the GT-48207). this ensures a proper reset condition throughout the device. in an unmanaged system, connect cclk to either the 25mhz 10/100 phy clock or to the 20mhz 10mbps phy clock. note: do not tie aclk to cclk, this will result in synchronization failures. tying aclk to cclk was recommended in previous documentation, however, this is incorrect information.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 114 revision 1.2 20. gt-482 xx p inout t ables , 208-pqfp table 65: gt-48212 pinout table (sorted by pin number) pin # signal name pin # signal name pin # signal name pin # signal name 1 ledclk 39 txde3 77 ddata[31] 115 vss 2 ledstb 40 rxde9 78 ddata[30] 116 vcc 3 leddata 41 txde9 79 ddata[29] 117 daddr[7] 4 cole0 42 rxde4 80 ddata[28] 118 daddr[8] 5 vcc 43 txde4 81 ddata[27] 119 mdio 6 vss 44 rxde10 82 ddata[26] 120 mdc 7 cole1 45 txde10 83 ddata[25] 121 crs0 8 cole2 46 rxde5 84 ddata[24] 122 col0 9 cole3 47 vss 85 vss 123 txd0[3] 10 cole4 48 txde5 86 vcc 124 txd0[2] 11 cole5 49 vcc 87 ddata[23] 125 txd0[1] 12 cole6 50 rxde11 88 ddata[22] 126 txd0[0] 13 cole7 51 txde11 89 ddata[21] 127 txen0 14 cole8 52 scan* 90 ddata[20] 128 rxdv0 15 vss 53 tristate* 91 ddata[19] 129 rxer0 16 sclk 54 endev* 92 vcc 130 vcc 17 vcc 55 vcc 93 vss 131 txclk0 18 cole9 56 vss 94 ddata[18] 132 vss 19 cole10 57 limit4* 95 ddata[17] 133 rxclk0 20 cole11 58 ddata[8] 96 vss 134 rxd0[3] 21 serlinkstat 59 ddata[9] 97 ddata[16] 135 rxd0[2] 22 linkstat0 60 ddata[10] 98 dqm 136 rxd0[1] 23 txene0 61 ddata[11] 99 we* 137 rxd0[0] 24 rxde0 62 ddata[12] 100 cas* 138 crs1 25 txde0 63 ddata[13] 101 ras* 139 col1 26 rxde6 64 ddata[14] 102 cs* 140 txd1[0] 27 txde6 65 vss 103 daddr[11] 141 txd1[1] 28 txde1 66 ddata[15] 104 daddr[10] 142 txd1[2] 29 rxde1 67 ddata[7] 105 vss 143 txd1[3] 30 vss 68 ddata[6] 106 vcc 144 txen1 31 rxde7 69 ddata[5] 107 daddr[9] 145 rxdv1 32 txde7 70 ddata[4] 108 daddr[0] 146 rxer1
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 115 33 rxde2 71 ddata[3] 109 daddr[1] 147 vss 34 aclk 72 ddata[2] 110 daddr[2] 148 txclk1 35 txde2 73 ddata[1] 111 daddr[3] 149 vcc 36 rxde8 74 vss 112 daddr[4] 150 rxclk1 37 txde8 75 vcc 113 daddr[5] 151 rxd1[0] 38 rxde3 76 ddata[0] 114 daddr[6] 152 rxd1[1] 153 rxd1[2] 167 ad[6] 181 ad[14] 195 ad[26] 154 rxd1[3] 168 vcc 182 ad[15] 196 ad[27] 155 rst* 169 vss 183 ad[16] 197 ad[28] 156 rdcen* 170 ad[7] 184 ad[17] 198 ad[29] 157 burstaddr[1] 171 vss 185 ad[18] 199 vss 158 burstaddr[2] 172 ad[8] 186 ad[19] 200 blast* 159 ad[0] 173 ad[9] 187 ad[20] 201 ad[30] 160 ad[1] 174 ad[10] 188 ad[21] 202 ad[31] 161 vss 175 ad[11] 189 vss 203 w/r* 162 vcc 176 ad[12] 190 vcc 204 ads* 163 ad[2] 177 ad[13] 191 ad[22] 205 vcc 164 ad[3] 178 vss 192 ad[23] 206 vss 165 ad[4] 179 cclk 193 ad[24] 207 ready* 166 ad[5] 180 vcc 194 ad[25] 208 int* table 66: gt-48208 pinout table (sorted by pin number) pin # signal name pin # signal name pin # signal name pin # signal name 1 ledclk 39 txde3 77 ddata[31] 115 vss 2 ledstb 40 rxde9 78 ddata[30] 116 vcc 3 leddata 41 txde9 79 ddata[29] 117 daddr[7] 4 cole0 42 rxde4 80 ddata[28] 118 daddr[8] 5 vcc 43 txde4 81 ddata[27] 119 mdio 6 vss 44 rxde10 82 ddata[26] 120 mdc 7 cole1 45 txde10 83 ddata[25] 121 crs0 8 cole2 46 vcc 2 84 ddata[24] 122 col0 9 cole3 47 vss 85 vss 123 txd0[3] table 65: gt-48212 pinout table (sorted by pin number) (continued) pin # signal name pin # signal name pin # signal name pin # signal name
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 116 revision 1.2 10 cole4 48 nc 86 vcc 124 txd0[2] 11 cole5 49 vcc 87 ddata[23] 125 txd0[1] 12 cole6 50 vcc 2 88 ddata[22] 126 txd0[0] 13 cole7 51 nc 89 ddata[21] 127 txen0 14 cole8 52 scan* 90 ddata[20] 128 rxdv0 15 vss 53 tristate* 91 ddata[19] 129 rxer0 16 sclk 54 endev* 92 vcc 130 vcc 17 vcc 55 vcc 93 vss 131 txclk0 18 cole9 56 vss 94 ddata[18] 132 vss 19 cole10 57 limit4* 95 ddata[17] 133 rxclk0 20 cole11 58 ddata[8] 96 vss 134 rxd0[3] 21 serlinkstat 59 ddata[9] 97 ddata[16] 135 rxd0[2] 22 linkstat0 60 ddata[10] 98 dqm 136 rxd0[1] 23 txene0 61 ddata[11] 99 we* 137 rxd0[0] 24 rxde0 62 ddata[12] 100 cas* 138 crs1 25 txde0 63 ddata[13] 101 ras* 139 col1 26 rxde6 64 ddata[14] 102 cs* 140 txd1[0] 27 txde6 65 vss 103 daddr[11] 141 txd1[1] 28 nc 1 66 ddata[15] 104 daddr[10] 142 txd1[2] 29 vcc 2 67 ddata[7] 105 vss 143 txd1[3] 30 vss 68 ddata[6] 106 vcc 144 txen1 31 vcc 2 69 ddata[5] 107 daddr[9] 145 rxdv1 32 nc 70 ddata[4] 108 daddr[0] 146 rxer1 33 rxde2 71 ddata[3] 109 daddr[1] 147 vss 34 aclk 72 ddata[2] 110 daddr[2] 148 txclk1 35 txde2 73 ddata[1] 111 daddr[3] 149 vcc 36 rxde8 74 vss 112 daddr[4] 150 rxclk1 37 txde8 75 vcc 113 daddr[5] 151 rxd1[0] 38 rxde3 76 ddata[0] 114 daddr[6] 152 rxd1[1] 153 rxd1[2] 167 ad[6] 181 ad[14] 195 ad[26] 154 rxd1[3] 168 vcc 182 ad[15] 196 ad[27] 155 rst* 169 vss 183 ad[16] 197 ad[28] 156 rdcen* 170 ad[7] 184 ad[17] 198 ad[29] 157 burstaddr[1] 171 vss 185 ad[18] 199 vss table 66: gt-48208 pinout table (sorted by pin number) (continued) pin # signal name pin # signal name pin # signal name pin # signal name
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 117 1. nc = no connect. do not connect this pin. 2. if users only want to design the board for the gt-48208, these pins can be tied directly to vcc. if users want to design the board for both the gt-48212 and the gt-48208, these pins should be pulled up to vcc through a resistor. galileo recom- mends using a 4.7kohm resistor value. 158 burstaddr[2] 172 ad[8] 186 ad[19] 200 blast* 159 ad[0] 173 ad[9] 187 ad[20] 201 ad[30] 160 ad[1] 174 ad[10] 188 ad[21] 202 ad[31] 161 vss 175 ad[11] 189 vss 203 w/r* 162 vcc 176 ad[12] 190 vcc 204 ads* 163 ad[2] 177 ad[13] 191 ad[22] 205 vcc 164 ad[3] 178 vss 192 ad[23] 206 vss 165 ad[4] 179 cclk 193 ad[24] 207 ready* 166 ad[5] 180 vcc 194 ad[25] 208 int* table 67: GT-48207 pinout table (sorted b y pin number) pin # signal name pin # signal name pin # signal name pin # signal name 1 ledclk 39 txde3 77 ddata[31] 115 vss 2 ledstb 40 rxde9 78 ddata[30] 116 vcc 3 leddata 41 txde9 79 ddata[29] 117 daddr[7] 4 cole0 42 rxde4 80 ddata[28] 118 daddr[8] 5 vcc 43 txde4 81 ddata[27] 119 mdio 6 vss 44 rxde10 82 ddata[26] 120 mdc 7 cole1 45 txde10 83 ddata[25] 121 crs0 8 cole2 46 vcc 2 84 ddata[24] 122 col0 9 cole3 47 vss 85 vss 123 txd0[3] 10 cole4 48 nc 86 vcc 124 txd0[2] 11 cole5 49 vcc 87 ddata[23] 125 txd0[1] 12 cole6 50 vcc 2 88 ddata[22] 126 txd0[0] 13 cole7 51 nc 89 ddata[21] 127 txen0 14 cole8 52 scan* 90 ddata[20] 128 rxdv0 15 vss 53 tristate* 91 ddata[19] 129 rxer0 16 sclk 54 endev* 92 vcc 130 vcc 17vcc55vcc93vss131txclk0 18 cole9 56 vss 94 ddata[18] 132 vss table 66: gt-48208 pinout table (sorted by pin number) (continued) pin # signal name pin # signal name pin # signal name pin # signal name
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 118 revision 1.2 19 cole10 57 limit4* 95 ddata[17] 133 rxclk0 20 cole11 58 ddata[8] 96 vss 134 rxd0[3] 21 serlinkstat 59 ddata[9] 97 ddata[16] 135 rxd0[2] 22 linkstat0 60 ddata[10] 98 dqm 136 rxd0[1] 23 txene0 61 ddata[11] 99 we* 137 rxd0[0] 24 rxde0 62 ddata[12] 100 cas* 138 crs1 25 txde0 63 ddata[13] 101 ras* 139 col1 26 rxde6 64 ddata[14] 102 cs* 140 txd1[0] 27 txde6 65 vss 103 daddr[11] 141 txd1[1] 28 nc 1 66 ddata[15] 104 daddr[10] 142 txd1[2] 29 vcc 2 67 ddata[7] 105 vss 143 txd1[3] 30 vss 68 ddata[6] 106 vcc 144 txen1 31 vcc 2 69 ddata[5] 107 daddr[9] 145 rxdv1 32 nc 70 ddata[4] 108 daddr[0] 146 rxer1 33 rxde2 71 ddata[3] 109 daddr[1] 147 vss 34 aclk 72 ddata[2] 110 daddr[2] 148 txclk1 35 txde2 73 ddata[1] 111 daddr[3] 149 vcc 36 rxde8 74 vss 112 daddr[4] 150 rxclk1 37 txde8 75 vcc 113 daddr[5] 151 rxd1[0] 38 rxde3 76 ddata[0] 114 daddr[6] 152 rxd1[1] 153 rxd1[2] 167 vcc 2 181 vcc 2 195 vcc 2 154 rxd1[3] 168 vcc 182 vcc 2 196 vcc 2 155 rst* 169 vss 183 vcc 2 197 vcc 2 156 vcc 2 170 vcc 2 184 vcc 2 198 vcc 2 157 vcc 2 171 vss 185 vcc 2 199 vss 158 vcc 2 172 vcc 2 186 vcc 2 200 vcc 2 159 vcc 2 173 vcc 2 187 vcc 2 201 vcc 2 160 vcc 2 174 vcc 2 188 vcc 2 202 vcc 2 161 vss 175 vcc 2 189 vss 203 vcc 2 162 vcc 176 vcc 2 190 vcc 204 vcc 2 163 vcc 2 177 vcc 2 191 vcc 2 205 vcc 164 vcc 2 178 vss 192 vcc 2 206 vss 165 vcc 2 179 cclk 3 193 vcc 2 207 nc 166 vcc 2 180 vcc 194 vcc 2 208 nc table 67: GT-48207 pinout table (sorted b y pin number) (continued) pin # signal name pin # signal name pin # signal name pin # signal name
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 119 1. nc = no connect. do not connect this pin. see text on building systems to accept gt-48212/208/207 devices 2. if users only want to design the board for the GT-48207, these pins can be tied directly to vcc. if users want to design the board for the GT-48207 and the gt-48208/212, these pins should be pulled up to vcc through a resistor. galileo rec- ommends using a 4.7kohm resistor value. 3. for the GT-48207, pin 179 (cclk) must be driven by a clock source slower than aclk. the 25mhz clock for the 10/100 phy or the 20mhz clock for the 10mbps phy is acceptable.
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 120 revision 1.2 21. dc c haracteristics - preliminary/subject to change ) table 68: absolute maximum ratings symbol parameter min. max. unit vcc supply voltage -0.3 4 v vi input voltage -0.3 5.5 v vo output voltage -0.3 5.5 v io output current 24 ma iik input protect diode current +-20 ma iok output protect diode current +-20 ma tc operating case temperature 0 70 c tstg storage temperature -40 125 c esd 2000 v table 69: recommended operating conditions symbol parameter min. typ. max. unit vcc supply voltage 3.15 3.3 3.45 v vi input voltage (all pins are 5v tolerant) 0 5.5 v vo output voltage 0 vcc v tc case operating temperature 0 70 c cin input capacitance 7.2 pf cout output capacitance 7.2 pf table 70: dc electrical characteristics over operatin g ran g e (tc=0-70 c; vcc=+3.3v, +/-5%) symbol parameter test condition min. typ. max. unit vih input high level guaranteed logic high level 2.0 5.5 v vil input low level guaranteed logic low level -0.5 0.8 v voh output high voltage ioh = 2 ma ioh = 4 ma ioh = 8 ma 2.4 v vol output low voltage iol = 2 ma iol = 4 ma iol = 8 ma 0.4 v iih input high current +-1 ua iil input low current +-1 ua
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 121 note: pullup/pulldown resistors are 45kohm minimum, 65kohm t y pical, 80kohm maximum. 21.1 thermal data table 71 shows the package thermal data for the gt-482xx. please contact galileo technology if you are in doubt as to thermal considerations for your system. iozh high impedance out- put current +-1 ua iozl high impedance out- put current +-1 ua vh input hysteresis icc operating current vcc = 3.45v f=66mhz 500 ma table 71: 208 pqfp thermal data parameter definition value q ja thermal resistance: junction to ambient, 0 ft/s airflow 25c/w q jc thermal resistance: junction to case, 0 ft/s airflow 5c/w t j operating junction temperature 100c table 70: dc electrical characteristics over operatin g ran g e (tc=0-70 c; vcc=+3.3v, +/-5%) symbol parameter test condition min. typ. max. unit
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 122 revision 1.2 22. ac t iming - target/subject to change notes: 1. all delays, setup, and hold times are referred to cclk rising edge, unless stated otherwise. 2. all outputs are specified for 50pf load table 72: cpu interface timin g s ( tc= 0-70c; vcc = +3.3v +/- 5% ) symbol signals description min max unit cclk cpu interface clock frequency 16 50 (lower than aclk) mhz cclk cpu interface clock duty cycle 40 60 % tsu ads*, blast*, burstaddr[1:0], ad[31:0], rdcen*, wr* cpu interface input signal setup time (rela- tive to cclk) 8ns thd ads*, blast*, burstaddr[1:0], ad[31:0], rdcen*, wr* cpu interface input signal hold time (rela- tive to cclk) 1ns tov ad[31:0], ready*, rdcen* cpu interface output (or i/o) output valid delay (relative to cclk) 210ns toz ad[31:0], ready*, rdcen* cpu interface output (or i/o) output float delay from drive (relative to cclk) 29ns tzo ad[31:0], ready*, rdcen* cpu interface output (or i/o) output drive delay from float (relative to cclk) 210ns table 73: switch en g ine interface timin g s ( tc= 0-70c; vcc = +3.3v +/- 5% ) symbol signals description min max unit aclk switch engine clock frequency 40 66 mhz aclk switch engine clock duty cycle 40 60 % tsu cole11-0 switch engine input signal setup time (rela- tive to aclk) 8ns thd colle11-0 switch engine input signal hold time (rela- tive to aclk) 1ns tsu ddata[31:0] sdram data setup time (relative to aclk) 2 ns thd ddata[31:0] sdram data hold time (relative to aclk) 1 ns tov cole11-0, cs*, daddr[11:0], ddata[31:0], cas*, dramwr*) ras*, dqm switch engine output (or i/o) output valid delay (relative to aclk) 38ns -
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 123 notes: 1. all delays, setup, and hold times are referred to aclk rising edge, unless stated otherwise. 2. all outputs are specified for 50pf load toz ddata[31:0], cole11-0 switch engine output (or i/o) output float delay from drive (relative to aclk) 29ns tzo ddata[31:0], cole11-0 switch engine output (or i/o) output drive delay from float (relative to aclk) 210ns table 74: mii, led and mdc/mdio timings ( tc= 0-70c; vcc = +3.3v +/- 5% ) symbol signals description min max unit rxclk mii receive clock frequency note : for applications requiring even lower frequencies please consult your local galileo fae. 2.5 25 (lower than aclk) mhz txclk mii transmit clock frequency note : for applications requiring even lower frequencies please consult your local galileo fae. 2.5 25 (lower than aclk) mhz rxclk mii receive clock frequency in expan- sion mode see note 2. 60 (lower than aclk) mhz txclk mii transmit clock frequency in expan- sion mode see note 2. 60 (lower than aclk) mhz tsu rxdv, rxer mii signal setup time with respect to rxclk 10 ns thd rxdv, rxer mii signal hold time with respect to rxclk 3ns tsu rxd[3:0] mii receive data setup time with respect to rxclk 6ns thd rxd[3:0] mii receive data hold time with respect to rxclk 3ns tov txen, txd[3:0] mii transmit output valid delay (relative to txclk) 210ns tsu linkstat0, serlink- stat link status for port 0 and serial link sta- tus setup with respect to ledclk 10 ns thd linkstat0, serlink- stat link status for port 0 and serial link sta- tus hold time with respect to ledclk 1ns table 73: switch en g ine interface timin g s ( tc= 0-70c; vcc = +3.3v +/- 5% ) ( continued ) symbol signals description min max unit
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 124 revision 1.2 notes: 1. all outputs are specified for 50pf load. 2. the expansion mii may run up to 60mhz, but must be lower then aclk by 3mhz. figure 28: serial clock waveform (sclk) tov leddata, ledstrobe output valid delay with respect to led- clk. note : see section 13.4 "led interface description" on page 57 regarding the relation between ledclk and these sig- nals. 3 * aclk clock cycles) + 2ns 3 * aclk clock cycles) + 10ns (or more for margin) ns tsu mdio setup time for mdio relative to mdc 40 ns thd mdio hold time for mdio relative to mdc 10 1 ns tov mdio mdio output valid from mdc 2 50 ns table 75: serial clock timings ( tc= 0-70c; vcc = +3.3v +/- 5% ) symbol signals description min max unit t1 sclk rise time 2 ns t2 sclk fall time 2 ns sclk frequency stability +/-50 ppm table 74: mii, led and mdc/mdio timings ( tc= 0-70c; vcc = +3.3v +/- 5% ) symbol signals description min max unit sclk voh vol t1 t2
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 125 figure 29: output delay from rising edge figure 30: input setup and hold figure 31: output delay from clock tov min clk output tov max valid tsu thd clk input tov min tov max clk output
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 126 revision 1.2 figure 32: output float and drive delay clk valid valid output toz tzo
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 127 23. p ackaging figure 33: 208 lead pqfp package outline table 76: 208 pqfp package dimensions millimeters symbol min. nom. max. a 1 0.05 0.25 0.50 a 2 3.17 3.32 3.47 b 0.10 0.20 0.30 c 0.10 0.15 0.20 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e0.50 a 1 he e hd d b a 2 l l 1 0.08(0.003) m y e c
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 128 revision 1.2 hd 30.35 30.60 30.85 he 30.35 30.60 30.85 l 0.450.600.75 l 1 1.30 y0.08 q0 7 table 76: 208 pqfp package dimensions (continued) millimeters
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 129 24. d ocument h istory table 77: document history document type rev. # date comments preliminary 0.8 9/97 first revision derived from rev 1.8 architectural specifica- tion. [mk] preliminary 0.9 10/15/97 last pre-silicon release. [mk] preliminary 0.91ip 12/8/97 first interim release after alpha silicon. changes made: 1. hol pin strappin g option ( ddata[31] removed. hol is controlled b y recbufthr strappin g option. note: this was wron g and chan g ed back in rev 0.913ip ( see below ) . 2. direction bits in general purpose control re g ister2 had the sense inverted. this is cor- rected in 0.91ip. 3. the 10m port control re g ister erroneousl y showed the fulldx bit as bein g sampled from txen. it is actuall y sampled from the txd pin for the port ( as shown elsewhere in the spec ) . 4. the polarit y of the link status bits in the status re g ister is different for the 10m and 100m ports. this has been added. 5. the port 13 control re g ister was shown in 0.9 as bein g at 0x100c instead of 0x1004 where it actuall y is. 6. the autopol bit in the 10m port control re g isters is now reserved. 7. the polarit y of cpu address bit 22 ( decodin g cpu access to memor y vs. re g isters ) was inverted in 0.9. this is fixed in 0.9ip. 8. the 10m port control re g ister now shows that the serial mode is sampled from ddata[23:0], not the txdel/txd pins as shown in 0.9. this was correct elsewhere in the spec. 9. 100mbit port control - 0x1000 - 0x100c. correc- tion: bit[1] fdx - this is confi g ured b y boot strap- pin g the daddr[7:6], daddr[7] for port13, daddr[6] port12. 10.global control re g ister - 0x04 correction: bit[4] hash table mode - default value is "1". 11. sm i r e g ister: 0x50 correction: bit[26]: opcode - this bit is cleared at reset. 12.serial parameters 100 re g ister: 0x78 correc- tion: bit[25:22]: reserved - these bits are cleared at reset. 13.cpu new address: 0x40 and 0x44. correction: bit[31:4] of address1 should be mac[47:20], bit[19:0] of address2 should be mac[19:0].
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 130 revision 1.2 14.better description of memor y arra y endian added in cpu section. 15.pin strappin g s deleted from pin descriptions and left onl y in reset confi g uration section. 16. clockin g restrictions added to ac timin g s. preliminary 0.911ip 12/9/97 1. flow control strappin g polarit y was corrected in the reset strappin g options table on pa g e66. preliminary 12/12/97 0.912ip 1. fixed some broken cross references. no func- tional chan g es. preliminary 0.913ip 1/5/98 1. corrected hol strappin g option back to ddata[31]. preliminary 0.92 1/14/98 1. pa g e 31: corrected ddata[27:26] definition for auto-ne g otiation control to a g ree with pa g e 58. tie pins high to enable, and low for disable. 2. pa g e 83: corrected fullduplexmode select to a g ree with pa g e 57 definition. should be ddata[25:24] not ddata[7:6]. 3. pa g e 63: corrected portctrlre g [0:3] offset from 0x400-0x454 to 0x400-0x40c. 4. pa g e 84: corrected ease re g ister offset from 0x1010-0x1018 to 0x1008-0x1010. 5. pa g e 83/84: added definition of 100m portctrl- re g [31:19] to table as reserved. 6. pa g e 81/82: added definition of 10m portctrl- re g [31:19] to table as reserved. preliminary 0.93 n/a 1. chan g ed all vccc to vcc; vssc to vss and vdd to vcc. 2. pa g e 27, section 7.3: operation of gt-48212 writin g new descriptor to the cpu_tx_hi/ low_desc re g ister is clarified. 3. pa g e 90. vih ( max ) corrected to read 5.5v from vdd+0.5v. 4. re g ister 0x54, vlan ethert y pe: added recom- mendation that it should be pro g rammed to 0x8100 for compliance with ieee specifications. table 77: document history (continued) document type rev. # date comments
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 131 preliminary 1.0 3/4/98 1. pa g e 10: corrected limit4 to be active high instead of active low. corrected direction of rdcen*/burstaddr[0] from input to input/output. corrected direction of txen[1:0] from input/out- put to output onl y . 2. pa g e 11: corrected description of rst* si g nal to be asserted for al least 10 mii clocks, not 10 s y s- tem clocks. corrected aclk description to a max of 66mhz, not 50mhz. 3. pa g e 12: removed reset pin definitions from addr[11:0] description and referred to table 16, reset pin strappin g options, on pa g e66. added reference to table 19, cpu mode selec- tion, on pa g e70for ras*. 4. pa g e 22: corrected a g in g bit definition. 5. pa g e 57: corrected polarit y of daddr[11] in reset pin strappin g options for back pressure enable. 6. chapter 18: corrected offset addresses for counters[3:0] and counters[7:4] in the re g ister map. general clean-up of re g ister definitions. provided polarit y and default values for all si g - nals. 7. pa g e 93: added q ja and q jc values to table 71. removed t j maximum value from table 71. 8. pa g e 95: corrected thd ( mii hold time ) values to be 3ns minimum, from 1ns maximum. 9. removed galileo technolo gy confidential doc- ument. preliminary 1.1 4/30/98 1. added gt-48208 and GT-48207 pinouts ( pa g e115 ) and information to create a unified datasheet. 2. added rv32364 information ( pa g e69 ) . 3. added additional a g in g information ( pa g e30 ) . table 77: document history (continued) document type rev. # date comments
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 132 revision 1.2 preliminary 1.2 1/27/99 1. applied new template and format. 2. added list of tables and figures. 3. added a block diagram illustrating a typical managed switch with two 100mbit ports + 12 10 mbit ports. 4. changed aclk max frequency to 66mhz and cclk max frequency to 50mhz. 5. cclk frequency must be higher than 25% of aclk and lower than total aclk. 6. changed rxclk and txclk on the expansion port to max 60mhz frequency . 7. added appendix a on page135, illustration of the igmp packet formats. 8. section 1.1 "fast ethernet ports" on page 9, added information about two galaxy devices connected with an expansion port. 9. section 1.6 "address recognition" on page 10, changed the number of different unicast mac addresses and unlimited multicast/broadcast mac addresses recognized by gt-482xx from 8000 to 8192, and (2000 changed to 2,024 in 1mbyte configu- ration). 10. the following changes were made to table 2, pin functions, on page 14: - symbol for dram address changed from addr[11:0] to daddr[11:0] - in the description for the txen[0] symbol: transmit enable, added that packet is transmitted on port 0 - corrected description "it should be driven at the fall- ing edge of the clock" to "it should be driven at the falling edge of the ledclk" - corrected description for the mdio symbol: man- agement data input/output. - corrected description for the ledclk symbol - added polarity information for link status and serial link status indication 11. table 4, gt-482xx dram address mapping, on page 24, changed 1mbyte address for cpu descrip- tors. 12. section 6.1 "forwarding mask" on page 26, added "when the gt-482xx performs new address learning, the forw[14:0] bits are set to 0x7fff (all 1's)". 13. section 1.6 "address recognition" on page 10, cor- rected note about the treatment of incoming pause packets when flow control is disabled. 14. section 4. "microarchitectural overview" on page 21, corrected fifo size in 10mbit port and 100mbit port units. 15. section 6.3 "address learning process" on page 27, added information specific to two device configura- tions. table 77: document history (continued) document type rev. # date comments
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 133 preliminary 1.2 1/27/99 16. section 7.4 "forwarding a packet from the cpu to the gt-482xx" on page 34, corrected information in step 5). 17. section 7.5 "intervention mode" on page 35, interven- tion mode is also supported by multicast. 18. section 8.11.2 "entering partition state" on page 40, in third case added "only for port configured to au mode". 19. section 8.12 "back pressure" on page 41, added information about packet transmit during bp. 20. section 8.15 "mii management interface (smi)" on page 42, added "delay time between two consecutive smi write transactions should be a least (4x64=256)mdc clock cycles." 21. section 9.6 "link integrity" on page 45, deleted auto polarity detection information, this feature is not sup- ported. 22. added section 9.15 "serial link status indication" on page 47, with waveform example. 23. section 9.7 "data blinder" on page 45, changed the default value from 6us to 32us. 24. section 9.9.2 "entering partition state" on page 46, added "however, a more aggressive backoff algo- rithm can be set if limit4 is activated" to 2nd bullet. 25. added figure 9: example of serial link status indica- tor of port 1 link fail on page 47. 26. section 11.2 "monitoring (sniffer) mode" on page 49, corrected information "in monitoring mode, the gt- 482xx sends all receive (including local traffic) and transmits packets to the cpu, or to another port in the same gt-482xx device which is assigned to be the sniffer. included information about multiple device configurations. 27. section 12.7 "enabling/disabling ease functionality" on page 52, added ease enabling/disabling algo- rithm. 28. section 13.4 "led interface description" on page 57, deleted "ledclk frequency during rst* is 33 mhz." 29. section 15.1 "configuration pins" on page 66, added recommendation to pull up the pins for unmanaged systems unless the user desires to set a specific fea- ture. 30. table 16, reset pin strapping options, on page 66, added pin burstaddr[1] and changed config- uration function of daddr[10]. table 77: document history (continued) document type rev. # date comments
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce 134 revision 1.2 preliminary 1.2 1/27/99 31. the following changes were made to table 18, cpu interface pin mappings, on page 70: - changed burstaddr[1:0] in i960jx to pull up - changed burstaddr[1:0] in coldfire to pull up - changed rdcen in coldfire to pull up - changed rdcen in rv32364 to pull up - header "burstaddr[1:0]" -> "burstaddr[2:1] - coldfire cpu mode (mcf5202) connected to da*[0] 32. section 16.6 "cpu interface applications" on page 71, added waveform information 33. added section 17.1 "dram configuration" and sec- tion 17.2 "dram initialization" on page 80. 34. table 23, global control, offset: 0x04, on page 84, added that initial value should be 0x1 for p-0/1/2 and 0x0 for p-3/4. 35. table 24, status register, offset: 0x08, on page 87, initial value [3] is sampled from dqm pin and not daddr[5]. 36. table 37, cpu enqueue1, offset: 0x38, on page 94 added "0-unicast" for mult bit function. 37. table 47 and table 48 on page 99, changed initial val- ues. 38. table 58, port control (10m ports), offset: 0x400- 0x40c, 0x800 - 0x80c, 0xc00 - 0xc0c, on page 102, changed bit 8 field from reserved to easeen. 39. table 59, port control 12 (100m ports), offset: 0x1000, on page 104, replaced reserved bit [3:2] with priority for expansion port. 40. added table 60, port control 13 (100m ports), offset: 0x1004, on page 106table 72, cpu interface tim- ings (tc= 0-70c; vcc = +3.3v +/- 5%), on page 122, corrected min frequency to 1 thd symbol. 41. table 73, switch engine interface timings (tc= 0- 70c; vcc = +3.3v +/- 5%), on page 122, corrected min frequency as 1 for thd symbol and changed aclk max frequency to 66mhz. 42. updated table 74, mii, led and mdc/mdio timings (tc= 0-70c; vcc = +3.3v +/- 5%), on page 123 43. added table 75, serial clock timings (tc= 0-70c; vcc = +3.3v +/- 5%), on page 124. 44. added figure 28: serial clock waveform (sclk) on page 124 45. deleted section 22 "functional waveforms", and included cpu waveform information in section 16.6 "cpu interface applications" on page 71 table 77: document history (continued) document type rev. # date comments
gt-482xx switched ethernet controllers for 10+10/100 basex galileo technology confidential -- do not reproduce revision 1.2 135 a ppendix a figure 34 illustrates the packet format of a standard ethernet v2 packet and an ieee 802.3 llc/snap. figure 34: ethernet packet format note: the above do not include the ieee 802.1 q/p tag. if desired, this 4-byte tag can be included in the format and is added immediately after the sa field. in this case, the maximum acceptable packet length is 1522 bytes (instead of 1518 bytes). destination add (da) source add (sa) length cntl 03 dsap aa ssap aa type data org code 00 crc 6 2 6 1 1 1 3 2 4 38-1492 802.3 mac 802.2 lcc 802.2 snap destination add (da) source add (sa) type data crc 6 2 6 4 46-1500 46-1500 bytes standard ethernet v2 packet standard ieee 802.3 llc/snap packet

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